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module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable;
assign c_load = reset | (Q == 4'd12 & enable == 1);
assign c_d = 4'd1;
count4 the_counter (clk, c_enable, c_load, c_d, Q);
endmodule
|
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
wire [3:0] q0, q1, q2;
assign OneHertz = {q0 == 4'd9 && q1 == 4'd9 && q2 == 4'd9};
assign c_enable = {q1 == 4'd9 && q0 == 4'd9, q0 == 4'd9, 1'b1};
bcdcount counter0 (clk, reset, c_enable[0], q0);
bcdcount counter1 (clk, reset, c_enable[1], q1);
bcdcount counter2 (clk, reset, c_enable[2], q2);
endmodule |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output reg [15:0] q);
assign ena = {q[11:8] == 4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd9, q[7:4] == 4'd9 && q[3:0] == 4'd9, q[3:0] == 4'd9};
BCD bcd0(clk,reset,1,q[3:0]);
BCD bcd1(clk,reset,ena[1],q[7:4]);
BCD bcd2(clk,reset,ena[2],q[11:8]);
BCD bcd3(clk,reset,ena[3],q[15:12]);
endmodule
module BCD (
input clk,
input reset,
input ena,
output reg [3:0] Q
);
always@(posedge clk) begin
if (reset)
Q <= 0;
else if (ena)
begin
if (Q == 4'd9)
Q <= 4'd0;
else
Q <= Q + 1'd1;
end
end
endmodule
|
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
always@(posedge clk)begin
if(reset)
pm = 0;
else
pm = ((hh[7:0]==8'h11)&&(ss[7:0]==8'h59)&&(mm[7:0]==8'h59))?~pm:pm;
end
wire inter1, inter2;
assign inter1 = (ss[7:0]==8'h59);
assign inter2 = (ss[7:0]==8'h59)&&(mm[7:0]==8'h59);
BCD60 s(clk, reset, ena, ss[7:0]);
BCD60 m(clk, reset, inter1, mm[7:0]);
BCD12 h(clk, reset, inter2, hh[7:0]);
endmodule
module BCD60 (input clk,input reset,input ena,output reg [7:0] Q);
always@(posedge clk) begin
if (reset)
Q <= 8'h0;
else if (ena) begin
if (Q == 8'h59)
Q <= 8'h0;
else begin
if (Q[3:0] == 4'd9) begin
Q[3:0] <= 0;
Q[7:4] <= Q[7:4] + 4'd1;
end
else
Q[3:0] <= Q[3:0] + 4'd1;
end
end
end
endmodule
module BCD12 (input clk,input reset,input ena,output reg [7:0] Q);
always@(posedge clk) begin
if (reset)
Q <= 8'h12;
else if (ena)
begin
if (Q == 8'h12)
Q <= 8'h1;
else begin
if (Q[3:0] == 4'd9) begin
Q[3:0] <= 0;
Q[7:4] <= Q[7:4] + 4'd1;
end
else
Q[3:0] <= Q[3:0] + 4'd1;
end
end
end
endmodule
|
//method 1
module top_module(
input clk,
input areset,
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
// Asynchronous reset: Notice the sensitivity list.
// The shift register has four modes:
// reset
// load
// enable shift
// idle -- preserve q (i.e., DFFs)
always @(posedge clk, posedge areset) begin
if (areset) // reset
q <= 0;
else if (load) // load
q <= data;
else if (ena) // shift is enabled
q <= q[3:1]; // Use vector part select to express a shift.
end
endmodule
//method 2
module top_module(
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always@(posedge clk or posedge areset)begin
if(areset)
q<=4'b0;
else if(load)
q<=data;
else if(ena)
q<={1'b0, q[3:1]};
else
q<=q;
end
endmodule
|
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
// This rotator has 4 modes:
// load
// rotate left
// rotate right
// do nothing
// I used vector part-select and concatenation to express a rotation.
// Edge-sensitive always block: Use non-blocking assignments.
always @(posedge clk) begin
if (load) // Load
q <= data;
else if (ena == 2'h1) // Rotate right
q <= {q[0], q[99:1]};
else if (ena == 2'h2) // Rotate left
q <= {q[98:0], q[99]};
end
endmodule
|
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always @(posedge clk) begin
if(load)
q <= data;
else if (ena)
begin
case(amount)
2'b00: q <= {q[62:0],1'b0};
2'b01: q <= {q[55:0],8'b0};
2'b10: q <= {q[63],q[63:1]};
2'b11: q <= {{8{q[63]}},q[63-:56]}; // q <= {{8{q[63]}},q[63:8]};
endcase
end
end
endmodule
|
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always@(posedge clk)begin
if(reset)
q <= 5'h1;
else
q <= {1'b0^q[0], q[4], q[3]^q[0], q[2], q[1]};
end
endmodule
/*
module top_module(
input clk,
input reset,
output reg [4:0] q);
reg [4:0] q_next; // q_next is not a register
// Convenience: Create a combinational block of logic that computes
// what the next value should be. For shorter code, I first shift
// all of the values and then override the two bit positions that have taps.
// A logic synthesizer creates a circuit that behaves as if the code were
// executed sequentially, so later assignments override earlier ones.
// Combinational always block: Use blocking assignments.
always @(*) begin
q_next = q[4:1]; // Shift all the bits. This is incorrect for q_next[4] and q_next[2]
q_next[4] = q[0]; // Give q_next[4] and q_next[2] their correct assignments
q_next[2] = q[3] ^ q[0];
end
// This is just a set of DFFs. I chose to compute the connections between the
// DFFs above in its own combinational always block, but you can combine them if you wish.
// You'll get the same circuit either way.
// Edge-triggered always block: Use non-blocking assignments.
always @(posedge clk) begin
if (reset)
q <= 5'h1;
else
q <= q_next;
end
endmodule
*/
|
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output reg [2:0] LEDR); // Q
wire clk = KEY[0];
wire L = KEY[1];
wire [2:0] d = (L)?SW:{LEDR[1]^LEDR[2],LEDR[0],LEDR[2]};
always @(posedge clk)begin
LEDR <= d;
end
endmodule
|
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] q_next;
always @(*) begin
q_next = q[31:1]; // Shift all the bits. This is incorrect for q_next[4] and q_next[2]
q_next[31] = q[0]; // Give q_next[4] and q_next[2] their correct assignments
q_next[21] = q[22] ^ q[0];
q_next[1] = q[2] ^ q[0];
q_next[0] = q[1] ^ q[0];
end
always @(posedge clk) begin
if (reset)
q <= 32'h1;
else
q <= q_next;
end
endmodule
|
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg [3:0] Q;
assign out = Q[0];
always@(posedge clk) begin
if (~resetn)
Q <= 4'd0;
else
Q <= {in,Q[3:1]};
end
endmodule
|
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
wire [3:0] w_input = {KEY[3],LEDR[3],LEDR[2],LEDR[1]};
generate
genvar i;
for(i=0;i<4;i=i+1) begin: muxdff
MUXDFF (
.clk(KEY[0]),
.w(w_input[i]),
.R(SW[i]),
.E(KEY[1]),
.L(KEY[2]),
.Q(LEDR[i])
);
end
endgenerate
endmodule
module MUXDFF (
input clk,
input w, R, E, L,
output Q
);
reg Q_r;
wire d_in = (L)?R:(E)?w:Q_r;
always@(posedge clk)begin
Q_r <= d_in;
end
assign Q = Q_r;
endmodule |
module top_module (
input clk,
input enable,
input S,
input A, B, C,
output reg Z
);
reg [7:0] q;
// The final circuit is a shift register attached to a 8-to-1 mux.
// Create a 8-to-1 mux that chooses one of the bits of q based on the three-bit number {A,B,C}:
// There are many other ways you could write a 8-to-1 mux
// (e.g., combinational always block -> case statement with 8 cases).
assign Z = q[ {A, B, C} ];
// Edge-triggered always block: This is a standard shift register (named q) with enable.
// When enabled, shift to the left by 1 (discarding q[7] and and shifting in S).
always @(posedge clk) begin
if (enable)
q <= {q[6:0], S};
end
endmodule
|
module top_module(
input clk,
input load,
input [511:0] data,
output reg [511:0] q);
always @(posedge clk) begin
if (load)
q <= data; // Load the DFFs with a value.
else begin
// At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
// and its right neighbour. Since the operation is the same for every
// bit position, it can be written as a single operation on vectors.
// The shifts are accomplished using part select and concatenation operators.
// left right
// neighbour neighbour
q <= {1'b0,q[511:1]} ^ {q[510:0], 1'b0} ;
end
end
endmodule |
module top_module(
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @(posedge clk) begin
if(load)
q <= data;
else
q <= q^{q[510:0],1'b0} | q & ~{1'b0,q[511:1]} ;
end
endmodule
|
module top_module(
input clk,
input load,
input [255:0] data,
output [255:0] q );
reg [255:0] temp;
wire [287:0] map = {temp[15:0],temp,temp[255:240]};
int count;
always@(posedge clk) begin
if(load) begin
q <= data;
end
else begin
for (int i = 16; i < 272; i = i+1) begin
if(i == 16 || i == 32 || i == 48 || i == 64 || i == 80 || i == 96 || i==112 || i==128 || i == 144
|| i == 160 || i == 176 || i == 192 || i == 208 || i == 224 || i == 240 || i == 256) begin
count = map[i+1]+map[i+15]+map[i+16]+map[i+17]+map[i+31]+map[i-1]+map[i-15]+map[i-16];
end
else if (i == 31 || i == 47 || i == 63 || i == 79 || i == 95 || i==111 || i==127 || i == 143
|| i == 159 || i == 175 || i == 191 || i == 207 || i == 223 || i == 239 || i == 255 || i == 271) begin
count = map[i-1]+map[i-15]+map[i-16]+map[i-17]+map[i-31]+map[i+1]+map[i+15]+map[i+16];
end
else begin
count = map[i+1]+map[i+15]+map[i+16]+map[i+17]+map[i-1]+map[i-15]+map[i-16]+map[i-17];
end
if(count == 2)
q[i-16] <= q[i-16];
else if(count == 3)
q[i-16] <= 1'b1;
else
q[i-16] <= 1'b0;
end
end
end
always@(negedge clk) begin
temp <= q;
end
endmodule
|
module top_module (
input clk,
input in,
input areset,
output out
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter A=0, B=1;
reg state; // Ensure state and next are big enough to hold the state encoding.
reg next;
// A finite state machine is usually coded in three parts:
// State transition logic
// State flip-flops
// Output logic
// It is sometimes possible to combine one or more of these blobs of code
// together, but be careful: Some blobs are combinational circuits, while some
// are clocked (DFFs).
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always@(*) begin
case (state)
A: next = in ? A : B;
B: next = in ? B : A;
endcase
end
// Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.
always @(posedge clk, posedge areset) begin
if (areset) state <= B; // Reset to state B
else state <= next; // Otherwise, cause the state to transition
end
// Combinational output logic. In this problem, an assign statement is the simplest.
// In more complex circuits, a combinational always block may be more suitable.
assign out = (state==B);
endmodule
|
module top_module (
input clk,
input areset,
input bump_left,
input bump_right,
output walk_left,
output walk_right
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter WL=0, WR=1;
reg state;
reg next;
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always@(*) begin
case (state)
WL: next = bump_left ? WR : WL;
WR: next = bump_right ? WL : WR;
endcase
end
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always @(posedge clk, posedge areset) begin
if (areset) state <= WL;
else state <= next;
end
// Combinational output logic. In this problem, an assign statement are the simplest.
// In more complex circuits, a combinational always block may be more suitable.
assign walk_left = (state==WL);
assign walk_right = (state==WR);
endmodule
|
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah );
parameter L=0,R=1,LF=2,RF=3;
reg [1:0] state, next_state;
always @(*) begin
case(state)
L: next_state = (~ground)? LF : (bump_left)? R : L;
R: next_state = (~ground)? RF : (bump_right)? L : R;
LF: next_state = (ground)? L : LF;
RF: next_state = (ground)? R : RF;
endcase
end
always @(posedge clk or posedge areset) begin
if (areset)
state <= L;
else
state <= next_state;
end
assign walk_left = (state == L);
assign walk_right = (state == R);
assign aaah = (state == LF) || (state == RF);
endmodule
|
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter L=0,R=1,LF=2,RF=3, LD=4, RD =5;
reg [2:0] state, next_state;
always @(*) begin
case(state)
L: next_state = (~ground)? LF : (dig)? LD : (bump_left)? R : L;
R: next_state = (~ground)? RF : (dig)? RD : (bump_right)? L : R;
LF: next_state = (ground)? L : LF;
RF: next_state = (ground)? R : RF;
LD: next_state = (ground)? LD : LF;
RD: next_state = (ground)? RD : RF;
endcase
end
always @ (posedge clk or posedge areset) begin
if(areset)
state <= L;
else
state <= next_state;
end
assign aaah = (state == LF) || (state == RF);
assign walk_left = (state == L);
assign walk_right = (state == R);
assign digging = (state == LD) || (state == RD);
endmodule
|
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter L=0,R=1,LF=2,RF=3, LD=4, RD =5, SP = 6;
reg [2:0] state, next_state;
int second;
always @(*) begin
case(state)
L: next_state = (~ground)? LF : (dig)? LD : (bump_left)? R : L;
R: next_state = (~ground)? RF : (dig)? RD : (bump_right)? L : R;
LF: next_state = (~ground)? LF : (second > 19)? SP : L;
RF: next_state = (~ground)? RF : (second > 19)? SP : R;
LD: next_state = (ground)? LD : LF;
RD: next_state = (ground)? RD : RF;
SP: next_state = SP;
endcase
end
always @ (posedge clk or posedge areset) begin
if(areset) begin
state <= L;
second = 0;
end
else begin
state <= next_state;
if ((state == LF) || (state == RF))
second = second + 1;
else if (second > 20)
second = 20;
else
second = 0; // have to reset counter
end
end
assign aaah = ((state == LF) || (state == RF)) ;
assign walk_left = (state == L);
assign walk_right = (state == R);
assign digging = ((state == LD) || (state == RD));
endmodule
|
module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
always@ (*) begin
next_state[0] = (state[0] | state[1] | state[2] | state[3] | state[4] | state[7] | state[8] | state[9]) & ~in;
next_state[1] = (state[8] | state[9] | state[0]) & in;
next_state[2] = state[1] & in;
next_state[3] = state[2] & in;
next_state[4] = state[3] & in;
next_state[5] = state[4] & in;
next_state[6] = state[5] & in;
next_state[7] = (state[6] | state[7]) & in;
next_state[8] = state[5] & ~in;
next_state[9] = state[6] & ~in;
end
assign out1 = state[8] || state[9];
assign out2 = state[7] || state[9];
endmodule
|
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done); //
parameter init=0, read=1, d = 2;
reg[1:0] state, next;
int cnt;
// State transition logic (combinational)
always @(*) begin
case(state)
init: next = (in[3])? read : init;
read: next = (cnt == 3)? d : read;
d: next = (in[3])? read : init;
endcase
end
// State flip-flops (sequential)
always@ (posedge clk) begin
if (reset) begin
state <= init;
cnt = 1;
end
else begin
state <= next;
if (next == read)
cnt = cnt + 1;
if (next == d)
cnt = 1;
end
end
// Output logic
assign done = (state == d);
endmodule
|
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //
parameter B1=0, B2=1, B3=2, d=3;
reg[1:0] state, next;
// FSM from fsm_ps2
always @(*) begin
case(state)
B1: next = (in[3])? B2:B1;
B2: next = B3;
B3: next = d;
d: next = (in[3])? B2:B1;
endcase
end
always @(posedge clk) begin
if (reset)
state <= B1;
else begin
state <= next;
case(next)
B2: out_bytes[23:16] = in;
B3: out_bytes[15:8] = in;
d: out_bytes[7:0] = in;
endcase
end
end
// New: Datapath to store incoming bytes.
assign done = (state == d);
endmodule
|
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter i=0, r=1, d=2, e=3;
reg[1:0] state, next;
int cnt;
always @(*) begin
case(state)
i: next = (~in)? r: i;
r: next = (cnt == 9 && in)? d : (cnt==9 && ~in)? e : r; // 9 for end bit
d: next = (~in)? r: i;
e: next = (in)? i : e;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= i;
cnt = 0; // 0 for start bit
end
else begin
state <= next;
if (next == r)
cnt = cnt + 1;
if (next == e || next == d)
cnt = 0;
end
end
assign done = (state == d);
endmodule
|
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter i=0, r=1, d=2, e=3;
reg[1:0] state, next;
int cnt;
always @(*) begin
case(state)
i: next = (~in)? r: i;
r: next = (cnt == 9 && in)? d : (cnt==9 && ~in)? e : r; // 9 for end bit
d: next = (~in)? r: i;
e: next = (in)? i : e;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= i;
cnt = 0; // 0 for start bit
end
else begin
state <= next;
if (next == r) begin
cnt = cnt + 1;
if (cnt > 1)
out_byte[cnt - 2] = in;
end
if (next == e || next == d) begin
cnt = 0;
end
end
end
assign done = (state == d);
endmodule
|
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
parameter i=0, r=1, d=2, e=3, dp=4;
reg[2:0] state, next;
reg odd;
parity p_check(clk,~(state == r), in, odd);
int cnt;
always @(*) begin
case(state)
i: next = (~in)? r: i;
r: next = (cnt == 9 && in == ~odd)? dp : (cnt==9 && ~(in==~odd))? e : r; // 9 for parity bit
dp: next = (in)? d:e; // parity check finish
d: next = (~in)? r: i;
e: next = (in)? i : e;
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= i;
cnt = 0; // 0 for start bit
end
else begin
state <= next;
if (next == r) begin
cnt = cnt + 1;
if (cnt > 1)
out_byte[cnt - 2] = in;
end
if (next == e || next == d) begin
cnt = 0;
end
end
end
assign done = (state == d);
endmodule
|
// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A=0, B=1;
reg present_state, next_state;
always @(posedge clk) begin
if (reset) begin
// Fill in reset logic
present_state <= B;
out = 1;
end else begin
case (present_state)
// Fill in state transition logic
A: next_state = (in)? A : B;
B: next_state = (in)? B : A;
endcase
// State flip-flops
present_state = next_state;
case (present_state)
// Fill in output logic
A: out = 0;
B: out = 1;
endcase
end
end
endmodule
|
module top_module(
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err);
parameter i=0, one=1, two=2, thr=3, four=4, fiv=5, six=6, er=7, ds=8, flg=9;
reg[3:0] state, next;
always@(*) begin
case(state)
i: next = (in)? one:i;
one: next = (in)? two:i;
two: next = (in)? thr:i;
thr: next = (in)? four:i;
four: next = (in)? fiv:i;
fiv: next = (in)? six:ds;
six: next = (in)? er:flg;
er: next = (in)? er:i;
ds: next = (in)? one:i;
flg: next = (in)? one:i;
endcase
end
always@(posedge clk) begin
if(reset)
state <= i;
else
state <= next;
end
assign disc = (state == ds);
assign flag = (state == flg);
assign err = (state == er);
endmodule
|
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z );
parameter a=0,b=1,c=2;
reg[1:0] state, next;
always@(*) begin
case(state)
a: next = (x)? b : a;
b: next = (x)? b : c;
c: next = (x)? b : a;
endcase
end
always@(posedge clk or negedge aresetn) begin
if(!aresetn)
state <= a;
else
state <= next;
end
assign z = (state == c) & x;
endmodule
/*
module top_module (
input clk,
input aresetn,
input x,
output reg z
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter S=0, S1=1, S10=2;
reg[1:0] state, next; // Make sure state and next are big enough to hold the state encodings.
// Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.
always@(posedge clk, negedge aresetn)
if (!aresetn)
state <= S;
else
state <= next;
// Combinational always block for state transition logic. Given the current state and inputs,
// what should be next state be?
// Combinational always block: Use blocking assignments.
always@(*) begin
case (state)
S: next = x ? S1 : S;
S1: next = x ? S1 : S10;
S10: next = x ? S1 : S;
default: next = 'x;
endcase
end
// Combinational output logic. I used a combinational always block.
// In a Mealy state machine, the output depends on the current state *and*
// the inputs.
always@(*) begin
case (state)
S: z = 0;
S1: z = 0;
S10: z = x; // This is a Mealy state machine: The output can depend (combinational) on the input.
default: z = 1'bx;
endcase
end
endmodule
*/
|
module top_module (
input clk,
input areset,
input x,
output z
);
parameter a=0, b=1, c=2;
reg[1:0] state,next;
always@(*) begin
case(state)
a: next = (x)? b : a;
b: next = (x)? c : b;
c: next = (x)? c : b;
endcase
end
always@(posedge clk or posedge areset) begin
if (areset)
state <= a;
else
state <= next;
end
assign z = (state == b);
endmodule
|
module top_module (
input clk,
input areset,
input x,
output z
);
parameter a=0,b=1;
reg state,next;
always@(*) begin
case(state)
a: next = (x)? b:a;
b: next = b;
endcase
end
always@(posedge clk or posedge areset) begin
if (areset)
state <= a;
else
state <= next;
end
assign z = (state == a) & x || (state == b) & ~x;
endmodule
|
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter a=0, b=1;
reg state, next;
always@(*) begin
case(state)
a: next = (s)? b : a;
b: next = b;
endcase
end
always@(posedge clk) begin
if (reset)
state <= a;
else
state <= next;
end
int clk_cnt;
reg[1:0] cnt;
always@(posedge clk) begin
if (reset || state == a) begin
clk_cnt = 0;
cnt = 0;
end
else begin
if (state == b) begin
if (clk_cnt < 3)
clk_cnt = clk_cnt + 1;
else begin // clk_cnt = 3, reset cnt first
clk_cnt = 1;
cnt = 0;
end
end
if(next == b) begin
cnt = cnt + w;
end
end
end
assign z = (cnt == 2'd2) && (clk_cnt == 3);
endmodule
|
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter A=0,B=1,C=2,D=3,E=4;
reg[2:0] state, next;
always@(*) begin
case(state)
A: next = (~x)? A : B;
B: next = (~x)? B : E;
C: next = (~x)? C : B;
D: next = (~x)? B : C;
E: next = (~x)? D : E;
endcase
end
always@(posedge clk) begin
if (reset)
state <= A;
else
state <= next;
end
assign z = (state == D) || (state == E);
endmodule
|
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg[2:0] state,next;
parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100;
always@(*) begin
case(y)
A: next = (~x)? A : B;
B: next = (~x)? B : E;
C: next = (~x)? C : B;
D: next = (~x)? B : C;
E: next = (~x)? D : E;
endcase
end
always@(posedge clk) begin
state <= next;
end
assign z = (y == D) || (y == E);
assign Y0 = next[0];
endmodule
|
module top_module (
input [3:1] y,
input w,
output Y2);
parameter E=3'b100, F=3'b101, D=3'b011, C=3'b010, B=3'b001;
assign Y2 = (y==B) || (y==F) || (y==C && w) || (y==E && w);
endmodule
|
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4);
assign Y2 = y[1] && ~w;
assign Y4 = (y[2] | y[3] | y[5] | y[6]) && w;
endmodule
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z);
parameter A=0,B=1,C=2,D=3,E=4,F=5;
reg[3:0] state,next;
always@(*) begin
case(state)
A: next = (w)? A:B;
B: next = (w)? D:C;
C: next = (w)? D:E;
D: next = (w)? A:F;
E: next = (w)? D:E;
F: next = (w)? D:C;
endcase
end
always@(posedge clk) begin
if(reset)
state <= A;
else
state <= next;
end
assign z = (state==E) || (state == F);
endmodule
|
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
OFF: next_state = (j)? ON:OFF;
ON: next_state = (k)? OFF:ON;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset)
state <= OFF;
else
state <= next_state;
end
// Output logic
assign out = (state == ON);
endmodule
|
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z);
parameter A=0,B=1,C=2,D=3,E=4,F=5;
reg[3:0] state,next;
always@(*) begin
case(state)
A: next = (~w)? A:B;
B: next = (~w)? D:C;
C: next = (~w)? D:E;
D: next = (~w)? A:F;
E: next = (~w)? D:E;
F: next = (~w)? D:C;
endcase
end
always@(posedge clk) begin
if(reset)
state <= A;
else
state <= next;
end
assign z = (state==E) || (state == F);
endmodule
|
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = (y[0]) & w;
assign Y3 = (y[1] | y[2] | y[4]| y[5]) & ~w;
endmodule
|
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
wire r1,r2,r3,g1,g2,g3;
assign {r3,r2,r1} = r;
assign g = {g3,g2,g1};
parameter A=0,B=1,C=2,D=3;
reg[1:0] state, next;
always@(*) begin
case(state)
A: next = (r1)? B : (r2) ? C : (r3)? D : A;
B: next = (r1)? B : A;
C: next = (r2)? C : A;
D: next = (r3)? D : A;
default next = A;
endcase
end
always@(posedge clk) begin
if (!resetn)
state <= A;
else
state <= next;
end
assign g1 = (state == B);
assign g2 = (state == C);
assign g3 = (state == D);
endmodule
|
module top_module(
input clk,
input reset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
OFF: next_state = (j)? ON:OFF;
ON: next_state = (k)? OFF:ON;
endcase
end
always @(posedge clk) begin
// State flip-flops with asynchronous reset
if (reset)
state <= OFF;
else
state <= next_state;
end
// Output logic
assign out = (state == ON);
endmodule
|
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
always@(*)begin
case(state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
assign out = (state == 2'd3);
// State transition logic: next_state = f(state, in)
// Output logic: out = f(state) for a Moore state machine
endmodule
|
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[A] & ~in | state[C] & ~in;
assign next_state[B] = state[A] & in | state[B] & in | state[D] & in;
assign next_state[C] = state[B] & ~in | state[D] & ~in;
assign next_state[D] = state[C] & in;
// Output logic:
assign out = state[D];
endmodule
|
module top_module(
input clk,
input in,
input areset,
output out); //
reg[1:0] state, next_state;
parameter A=0, B=1, C=2, D=3;
// State transition logic
always@(*)begin
case(state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
// State flip-flops with asynchronous reset
always@(posedge clk or posedge areset) begin
if(areset)
state <= A;
else
state <= next_state;
end
// Output logic
assign out = state==D;
endmodule
|
module top_module(
input clk,
input in,
input reset,
output out); //
reg[1:0] state, next_state;
parameter A=0, B=1, C=2, D=3;
// State transition logic
always@(*)begin
case(state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: next_state = in ? D : A;
D: next_state = in ? B : C;
endcase
end
// State flip-flops with synchronous reset
always@(posedge clk) begin
if(reset)
state <= A;
else
state <= next_state;
end
// Output logic
assign out = (state==D);
endmodule
|
module top_module (
input clk,
input reset,
output reg [9:0] q);
always @(posedge clk) begin
if (reset)
q <= 0;
else if ( q == 10'd999)
q <= 0;
else
q <= q + 1;
end
endmodule
|
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q);
always@(posedge clk)begin
if(shift_ena)begin
q <= {q[2:0], data};
end
else if(count_ena)begin
q <= q - 1'b1;
end
end
endmodule
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting);
parameter A=0,B=1,C=2,D=3,E=4;
reg[2:0] state,next;
always@(*) begin
case(state)
A: next = (data)? B:A;
B: next = (data)? C:A;
C: next = (data)? C:D;
D: next = (data)? E:A;
E: next = (reset)? A:E;
endcase
end
always@(posedge clk) begin
if (reset)
state <= A;
else
state <= next;
end
assign start_shifting = (state == E);
endmodule
|
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena);
parameter A=0,B=1,C=2,D=3,E=4;
reg[2:0] state, next;
always@(*) begin
case(state)
A: next = (reset)? B:A;
B: next = (reset)? B:C;
C: next = (reset)? B:D;
D: next = (reset)? B:E;
E: next = (reset)? B:A;
endcase
end
always@(posedge clk) begin
if (reset)
state <= B;
else
state <= next;
end
assign shift_ena = (state != A);
endmodule
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack );
parameter S=0,S1=1,S11=2,S110=3, B0=4, B1=5, B2=6, B3=7, cnt=8, hold=9;
reg[3:0] state, next;
always@ (*) begin
case(state)
S: next = (data)? S1 : S;
S1: next = (data)? S11: S;
S11: next = (~data)? S110:S11;
S110: next = (data)? B0 : S;
B0: next = B1;
B1: next = B2;
B2: next = B3;
B3: next = cnt;
cnt: next = (done_counting)? hold:cnt;
hold: next = (ack)? S:hold;
endcase
end
always@(posedge clk) begin
if (reset)
state <= S;
else
state <= next;
end
assign shift_ena = (state == B0) || (state == B1) || (state == B2) || (state == B3);
assign counting = (state == cnt);
assign done = (state == hold);
endmodule
|
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack );
parameter S=0,S1=1,S11=2,S110=3, B0=4, B1=5, B2=6, B3=7, cnt=8, delay_cnt=9, last_cnt=10, hold=11;
reg[3:0] state, next, delay;
reg[9:0] thousand;
reg[3:0] counter;
always@ (*) begin
case(state)
S: next = (data)? S1 : S;
S1: next = (data)? S11: S;
S11: next = (~data)? S110:S11;
S110: next = (data)? B0 : S;
B0: begin next = B1;
delay[3] = data;
end
B1: begin next = B2;
delay[2] = data;
end
B2: begin next = B3;
delay[1] = data;
end
B3: begin next = cnt;
delay[0] = data;
end
cnt: next = (delay == 4'd0)? last_cnt : (thousand == 10'd998)? delay_cnt : cnt;
delay_cnt: next = (counter == 4'd1)? last_cnt : cnt; // one clock count
last_cnt: next = (thousand == 10'd999)? hold:last_cnt;
hold: next = (ack)? S:hold;
endcase
end
always@ (posedge clk) begin
if (state == B3) begin
counter <= {delay[3:1],data};
thousand <= 0;
end
if (state == cnt || state == last_cnt)
thousand <= thousand + 1'b1;
if (state == delay_cnt) begin
thousand <= 0;
counter <= counter - 1'b1;
end
end
always@(posedge clk) begin
if (reset)
state <= S;
else begin
state <= next;
end
end
assign counting = (state == cnt) || (state == delay_cnt) || (state == last_cnt);
assign done = (state == hold);
assign count = counter;
endmodule
|
module top_module(
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;
assign B3_next = state[B2];
assign S_next = ~d & state[S] | ~d & state[S1] | ~d & state[S110] | ack & state[Wait];
assign S1_next = d & state[S];
assign Count_next = state[B3] | ~done_counting & state[Count];
assign Wait_next = done_counting & state[Count] | ~ack & state[Wait];
assign done = state[Wait];
assign counting = state[Count];
assign shift_ena = state[B0] | state[B1] | state[B2] |state[B3];
endmodule
|
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// 1. A mux coded as (~sel & a) | (sel & b) does not work for vectors.
// This is because these are bitwise operators, and sel is only a 1 bit wide quantity,
// which leaves the upper bits of a and b zeroed. It is possible to code it using
// the replication operator, but this is somewhat difficult to read:
// ( {8{~sel}} & a ) | ( {8{sel}} & b )
// 2. The simulation waveform shows that when sel = 1, a should be selected. This
// is flipped in the suggested code.
assign out = sel ? a : b;
endmodule
|
module top_module (input a, input b, input c, output out);//
wire and_out;
andgate inst1(and_out, a, b, c, 1, 1 );
assign out = ~and_out;
endmodule
|
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out ); //
wire [7:0] out1, out2;
mux2 mux0 ( sel[0], a, b, out1 );
mux2 mux1 ( sel[0], c, d, out2 );
mux2 mux2 ( sel[1], out1, out2, out );
endmodule
|
// synthesis verilog_input_version verilog_2001
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
);//
always @(*) begin
case (do_sub)
0: out = a+b;
1: out = a-b;
endcase
result_is_zero = (out == 0);
end
endmodule
|
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
);
// A combinational always block.
always @(*) begin
out = 0; // To avoid latches, give the outputs a default assignment
valid = 1; // then override them in the case statement. This is less
// code than assigning a value to every variable for every case.
case (code)
8'h45: out = 0;
8'h16: out = 1;
8'h1e: out = 2;
8'h26: out = 3; // 8'd26 is 8'h1a
8'h25: out = 4;
8'h2e: out = 5;
8'h36: out = 6;
8'h3d: out = 7;
8'h3e: out = 8;
8'h46: out = 9;
default: valid = 0;
endcase
end
endmodule
|
module top_module (
input a,
input b,
output q
);
// This is a combinational circuit with one gate. The truth table
// can be found by looking at the simulation waveforms.
assign q = a & b;
endmodule
|
module top_module (
input clk,
input a,
input b,
output q,
output state );
always @(posedge clk) begin
if (a == b)
state <= a;
end
assign q = a^b^state;
endmodule
|
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = ~(a^b^c^d); // Fix me
endmodule
|
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b & (d | c) | a & (c | d); // Fix me
endmodule
|
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = b|c; // Fix me
endmodule
|
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q );
always @(*) begin
case(c)
4'd0: q = b;
4'd1: q = e;
4'd2: q = a;
4'd3: q = d;
default: q = 4'hf;
endcase
end
endmodule
|
module top_module (
input [2:0] a,
output [15:0] q );
always@(*)begin
case(a)
0: q = 16'h1232;
1: q = 16'haee0;
2: q = 16'h27d4;
3: q = 16'h5a0e;
4: q = 16'h2066;
5: q = 16'h64ce;
6: q = 16'hc526;
7: q = 16'h2f19;
endcase
end
endmodule
|
module top_module (
input clk,
input a,
output q );
always @(posedge clk) begin
q <= ~a;
end
endmodule
|
module top_module (
input clock,
input a,
output p,
output q );
always@(*)begin
if(clock)begin
p = a;
end
end
always@(negedge clock)begin
q <= p;
end
endmodule
|
module top_module (
input clk,
input a,
output [3:0] q );
always @(posedge clk) begin
if (a)
q <= 4'd4;
else begin
if (q == 4'd6)
q <= 0;
else
q <= q + 1;
end
end
endmodule
|
module top_module ( );
reg clk;
dut clock(clk);
initial begin
clk = 1'b0;
forever
#5
clk = ~clk;
end
/*
initial begin
clk = 1'b0;
end
always begin
#5
clk = ~clk;
end
*/
endmodule
|
module top_module ( output reg A, output reg B );//
// generate input patterns here
initial begin
A = 1'b0;
B = 1'b0;
#10;
A = 1'b1;
#5
B = 1'b1;
#5
A = 1'b0;
#20
B = 1'b0;
end
endmodule
|
module top_module();
reg [1:0] in;
initial begin
in = 2'b00;
#10
in = 2'b01;
#10
in = 2'b10;
#10
in = 2'b11;
end
wire out;
andgate u_and(in,out);
endmodule
|
module top_module();
reg clk;
reg in;
reg[2:0] s;
wire out;
initial begin
clk = 1'b0;
forever
#5
clk = ~clk;
end
initial begin
in = 1'b0;
s = 3'd2;
#10;
in = 1'b0;
s = 3'd6;
#10;
in = 1'b1;
s = 3'd2;
#10;
in = 1'b0;
s = 3'd7;
#10;
in = 1'b1;
s = 3'd0;
#30;
in = 1'b0;
s = 3'd0;
end
q7 u_q7(clk, in, s, out);
endmodule
|
module top_module ();
reg clk;
reg reset;
reg t;
wire q;
initial begin
clk = 0;
reset = 0;
t = 0;
#3;
reset = 1'b1;
#10;
reset = 1'b0;
end
always begin
#5
clk = ~clk;
end
always@(posedge clk)begin
if(reset)begin
t <= 1'b0;
end
else begin
t <= 1'b1;
end
end
tff u_tff(clk,reset,t,q);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Codec Register Access Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_cra.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_cra.v,v $
// Revision 1.3 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_cra(clk, rst,
crac_we, crac_din, crac_out,
crac_wr_done, crac_rd_done,
valid, out_slt1, out_slt2,
in_slt2,
crac_valid, crac_wr
);
input clk, rst;
input crac_we;
output [15:0] crac_din;
input [31:0] crac_out;
output crac_wr_done, crac_rd_done;
input valid;
output [19:0] out_slt1;
output [19:0] out_slt2;
input [19:0] in_slt2;
output crac_valid;
output crac_wr;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg crac_wr;
reg crac_rd;
reg crac_rd_done;
reg [15:0] crac_din;
reg crac_we_r;
reg valid_r;
wire valid_ne;
wire valid_pe;
reg rdd1, rdd2, rdd3;
////////////////////////////////////////////////////////////////////
//
// Codec Register Data Path
//
// Control
assign out_slt1[19] = crac_out[31];
assign out_slt1[18:12] = crac_out[22:16];
assign out_slt1[11:0] = 12'h0;
// Write Data
assign out_slt2[19:4] = crac_out[15:0];
assign out_slt2[3:0] = 4'h0;
// Read Data
always @(posedge clk or negedge rst)
begin
if(!rst) crac_din <= #1 16'h0;
else
if(crac_rd_done) crac_din <= #1 in_slt2[19:4];
end
////////////////////////////////////////////////////////////////////
//
// Codec Register Access Tracking
//
assign crac_valid = crac_wr | crac_rd;
always @(posedge clk)
crac_we_r <= #1 crac_we;
always @(posedge clk or negedge rst)
if(!rst) crac_wr <= #1 1'b0;
else
if(crac_we_r & !crac_out[31]) crac_wr <= #1 1'b1;
else
if(valid_ne) crac_wr <= #1 1'b0;
assign crac_wr_done = crac_wr & valid_ne;
always @(posedge clk or negedge rst)
if(!rst) crac_rd <= #1 1'b0;
else
if(crac_we_r & crac_out[31]) crac_rd <= #1 1'b1;
else
if(rdd1 & valid_pe) crac_rd <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) rdd1 <= #1 1'b0;
else
if(crac_rd & valid_ne) rdd1 <= #1 1'b1;
else
if(!crac_rd) rdd1 <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) rdd2 <= #1 1'b0;
else
if( (crac_rd & valid_ne) | (!rdd3 & rdd2) ) rdd2 <= #1 1'b1;
else
if(crac_rd_done) rdd2 <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) rdd3 <= #1 1'b0;
else
if(rdd2 & valid_pe) rdd3 <= #1 1'b1;
else
if(crac_rd_done) rdd3 <= #1 1'b0;
always @(posedge clk)
crac_rd_done <= #1 rdd3 & valid_pe;
always @(posedge clk)
valid_r <= #1 valid;
assign valid_ne = !valid & valid_r;
assign valid_pe = valid & !valid_r;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller Definitions ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_defines.v,v 1.5 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_defines.v,v $
// Revision 1.5 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.4 2002/03/11 03:21:22 rudi
//
// - Added defines to select fifo depth between 4, 8 and 16 entries.
//
// Revision 1.3 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:14 rudi
// Initial Checkin
//
//
//
//
`timescale 1ns / 10ps
/////////////////////////////////////////////////////////////////////
// This AC97 Controller supports up to 6 Output and 3 Input Channels.
// Comment out the define statement for which channels you do not wish
// to support in your implementation. The main Left and Right channels
// are always supported.
// Surround Left + Right
`define AC97_SURROUND 1
// Center Channel
`define AC97_CENTER 1
// LFE Channel
`define AC97_LFE 1
// Stereo Input
`define AC97_SIN 1
// Mono Microphone Input
`define AC97_MICIN 1
/////////////////////////////////////////////////////////////////////
//
// This define selects how the WISHBONE interface determines if
// the internal register file is selected.
// This should be a simple address decoder. "wb_addr_i" is the
// WISHBONE address bus (32 bits wide).
`define AC97_REG_SEL (wb_addr_i[31:29] == 3'h0)
/////////////////////////////////////////////////////////////////////
//
// This is a prescaler that generates a pulse every 250 nS.
// The value here should one less than the actually calculated
// value.
// For a 200 MHz wishbone clock, this value is 49 (50-1).
`define AC97_250_PS 6'h31
/////////////////////////////////////////////////////////////////////
//
// AC97 Cold reset Must be asserted for at least 1uS. The AC97
// controller will stretch the reset pulse to at least 1uS.
// The reset timer is driven by the AC97_250_PS prescaler.
// This value should probably be never changed. Adjust the
// AC97_250_PS instead.
`define AC97_RST_DEL 3'h4
/////////////////////////////////////////////////////////////////////
//
// This value indicates for how long the resume signaling (asserting sync)
// should be done. This counter is driven by the AC97_250_PS prescaler.
// This value times 250nS is the duration of the resume signaling.
// The actual value must be incremented by one, as we do not know
// the current state of the prescaler, and must somehow insure we
// meet the minimum 1uS length. This value should probably be never
// changed. Modify the AC97_250_PS instead.
`define AC97_RES_SIG 3'h5
/////////////////////////////////////////////////////////////////////
//
// If the bit clock is absent for at least two "predicted" bit
// clock periods (163 nS) we should signal "suspended".
// This value defines how many WISHBONE cycles must pass without
// any change on the bit clock input before we signal "suspended".
// For a 200 MHz WISHBONE clock this would be about (163/5) 33 cycles.
`define AC97_SUSP_DET 6'h21
/////////////////////////////////////////////////////////////////////
//
// Select FIFO Depth. For most applications a FIFO depth of 4 should
// be sufficient. For systems with slow interrupt processing or slow
// DMA response or systems with low internal bus bandwidth you might
// want to increase the FIFO sizes to reduce the interrupt/DMA service
// request frequencies.
// Service request frequency can be calculated as follows:
// Channel bandwidth / FIFO size = Service Request Frequency
// For Example: 48KHz / 4 = 12 kHz
//
// Select Input FIFO depth by uncommenting ONE of the following define
// statements:
`define AC97_IN_FIFO_DEPTH_4
//`define AC97_IN_FIFO_DEPTH_8
//`define AC97_IN_FIFO_DEPTH_16
//
// Select Output FIFO depth by uncommenting ONE of the following define
// statements:
`define AC97_OUT_FIFO_DEPTH_4
//`define AC97_OUT_FIFO_DEPTH_8
//`define AC97_OUT_FIFO_DEPTH_16
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// DMA Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_dma_if.v,v 1.4 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_dma_if.v,v $
// Revision 1.4 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.3 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_dma_if(clk, rst,
o3_status, o4_status, o6_status, o7_status, o8_status, o9_status,
o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty,
i3_status, i4_status, i6_status,
i3_full, i4_full, i6_full,
oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
ic0_cfg, ic1_cfg, ic2_cfg,
dma_req, dma_ack);
input clk, rst;
input [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;
input o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;
input [1:0] i3_status, i4_status, i6_status;
input i3_full, i4_full, i6_full;
input [7:0] oc0_cfg;
input [7:0] oc1_cfg;
input [7:0] oc2_cfg;
input [7:0] oc3_cfg;
input [7:0] oc4_cfg;
input [7:0] oc5_cfg;
input [7:0] ic0_cfg;
input [7:0] ic1_cfg;
input [7:0] ic2_cfg;
output [8:0] dma_req;
input [8:0] dma_ack;
////////////////////////////////////////////////////////////////////
//
// DMA Request Modules
//
ac97_dma_req u0(.clk( clk ),
.rst( rst ),
.cfg( oc0_cfg ),
.status( o3_status ),
.full_empty( o3_empty ),
.dma_req( dma_req[0] ),
.dma_ack( dma_ack[0] )
);
ac97_dma_req u1(.clk( clk ),
.rst( rst ),
.cfg( oc1_cfg ),
.status( o4_status ),
.full_empty( o4_empty ),
.dma_req( dma_req[1] ),
.dma_ack( dma_ack[1] )
);
`ifdef AC97_CENTER
ac97_dma_req u2(.clk( clk ),
.rst( rst ),
.cfg( oc2_cfg ),
.status( o6_status ),
.full_empty( o6_empty ),
.dma_req( dma_req[2] ),
.dma_ack( dma_ack[2] )
);
`else
assign dma_req[2] = 1'b0;
`endif
`ifdef AC97_SURROUND
ac97_dma_req u3(.clk( clk ),
.rst( rst ),
.cfg( oc3_cfg ),
.status( o7_status ),
.full_empty( o7_empty ),
.dma_req( dma_req[3] ),
.dma_ack( dma_ack[3] )
);
ac97_dma_req u4(.clk( clk ),
.rst( rst ),
.cfg( oc4_cfg ),
.status( o8_status ),
.full_empty( o8_empty ),
.dma_req( dma_req[4] ),
.dma_ack( dma_ack[4] )
);
`else
assign dma_req[3] = 1'b0;
assign dma_req[4] = 1'b0;
`endif
`ifdef AC97_LFE
ac97_dma_req u5(.clk( clk ),
.rst( rst ),
.cfg( oc5_cfg ),
.status( o9_status ),
.full_empty( o9_empty ),
.dma_req( dma_req[5] ),
.dma_ack( dma_ack[5] )
);
`else
assign dma_req[5] = 1'b0;
`endif
`ifdef AC97_SIN
ac97_dma_req u6(.clk( clk ),
.rst( rst ),
.cfg( ic0_cfg ),
.status( i3_status ),
.full_empty( i3_full ),
.dma_req( dma_req[6] ),
.dma_ack( dma_ack[6] )
);
ac97_dma_req u7(.clk( clk ),
.rst( rst ),
.cfg( ic1_cfg ),
.status( i4_status ),
.full_empty( i4_full ),
.dma_req( dma_req[7] ),
.dma_ack( dma_ack[7] )
);
`else
assign dma_req[6] = 1'b0;
assign dma_req[7] = 1'b0;
`endif
`ifdef AC97_MICIN
ac97_dma_req u8(.clk( clk ),
.rst( rst ),
.cfg( ic2_cfg ),
.status( i6_status ),
.full_empty( i6_full ),
.dma_req( dma_req[8] ),
.dma_ack( dma_ack[8] )
);
`else
assign dma_req[8] = 1'b0;
`endif
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// DMA Request Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_dma_req.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_dma_req.v,v $
// Revision 1.3 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:16 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_dma_req(clk, rst, cfg, status, full_empty, dma_req, dma_ack);
input clk, rst;
input [7:0] cfg;
input [1:0] status;
input full_empty;
output dma_req;
input dma_ack;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg dma_req_d;
reg dma_req_r1;
reg dma_req;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(cfg or status or full_empty)
case(cfg[5:4]) // synopsys parallel_case full_case
// REQ = Ch_EN & DMA_EN & Status
// 1/4 full/empty
2'h2: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status == 2'h0));
// 1/2 full/empty
2'h1: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status[1] == 1'h0));
// 3/4 full/empty
2'h0: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status < 2'h3));
2'h3: dma_req_d = cfg[0] & cfg[6] & full_empty;
endcase
always @(posedge clk)
dma_req_r1 <= #1 dma_req_d & !dma_ack;
always @(posedge clk or negedge rst)
if(!rst) dma_req <= #1 1'b0;
else
if(dma_req_r1 & dma_req_d & !dma_ack) dma_req <= #1 1'b1;
else
if(dma_ack) dma_req <= #1 1'b0;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// FIFO Control Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_fifo_ctrl.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_fifo_ctrl.v,v $
// Revision 1.3 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:49 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_fifo_ctrl( clk,
valid, ch_en, srs, full_empty, req, crdy,
en_out, en_out_l
);
input clk;
input valid;
input ch_en; // Channel Enable
input srs; // Sample Rate Select
input full_empty; // Fifo Status
input req; // Codec Request
input crdy; // Codec Ready
output en_out; // Output read/write pulse
output en_out_l; // Latched Output
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg en_out_l, en_out_l2;
reg full_empty_r;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
if(!valid) full_empty_r <= #1 full_empty;
always @(posedge clk)
if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) )
en_out_l <= #1 1'b1;
else
if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) )
en_out_l <= #1 1'b0;
always @(posedge clk)
en_out_l2 <= #1 en_out_l & valid;
assign en_out = en_out_l & !en_out_l2 & valid;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Interrupt Logic ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_int.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_int.v,v $
// Revision 1.3 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:18 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_int(clk, rst,
// Register File Interface
int_set,
// FIFO Interface
cfg, status, full_empty, full, empty, re, we
);
input clk, rst;
output [2:0] int_set;
input [7:0] cfg;
input [1:0] status;
input full_empty, full, empty, re, we;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [2:0] int_set;
////////////////////////////////////////////////////////////////////
//
// Interrupt Logic
//
always @(posedge clk or negedge rst)
if(!rst) int_set[0] <= #1 1'b0;
else
case(cfg[5:4]) // synopsys parallel_case full_case
// 1/4 full/empty
2'h2: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'h0));
// 1/2 full/empty
2'h1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'h0));
// 3/4 full/empty
2'h0: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'h3));
2'h3: int_set[0] <= #1 cfg[0] & full_empty;
endcase
always @(posedge clk or negedge rst)
if(!rst) int_set[1] <= #1 1'b0;
else
if(empty & re) int_set[1] <= #1 1'b1;
always @(posedge clk or negedge rst)
if(!rst) int_set[2] <= #1 1'b0;
else
if(full & we) int_set[2] <= #1 1'b1;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Output FIFO ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_in_fifo.v,v 1.5 2002/11/14 17:10:12 rudi Exp $
//
// $Date: 2002/11/14 17:10:12 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_in_fifo.v,v $
// Revision 1.5 2002/11/14 17:10:12 rudi
// Fixed a bug in the IN-FIFO - 18 bit samples where not alligned correctly.
//
// Revision 1.4 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.3 2002/03/11 03:21:22 rudi
//
// - Added defines to select fifo depth between 4, 8 and 16 entries.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:14 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
`ifdef AC97_IN_FIFO_DEPTH_4
// 4 entry deep verion of the input FIFO
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [19:0] din;
input we;
output [31:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:3];
reg [31:0] dout;
reg [3:0] wp;
reg [2:0] rp;
wire [3:0] wp_p1;
reg [1:0] status;
reg [15:0] din_tmp1;
reg [31:0] din_tmp;
wire m16b;
reg full, empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 4'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);
always @(posedge clk)
if(!en) rp <= #1 3'h0;
else
if(re) rp <= #1 rp + 3'h1;
always @(posedge clk)
status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);
always @(posedge clk)
empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
always @(posedge clk)
full <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]);
// Fifo Output
always @(posedge clk)
dout <= #1 mem[ rp[1:0] ];
// Fifo Input Half Word Latch
always @(posedge clk)
if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
always @(mode or din_tmp1 or din)
case(mode) // synopsys parallel_case full_case
2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output
2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
endcase
always @(posedge clk)
if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;
endmodule
`endif
`ifdef AC97_IN_FIFO_DEPTH_8
// 8 entry deep verion of the input FIFO
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [19:0] din;
input we;
output [31:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:7];
reg [31:0] dout;
reg [4:0] wp;
reg [3:0] rp;
wire [4:0] wp_p1;
reg [1:0] status;
reg [15:0] din_tmp1;
reg [31:0] din_tmp;
wire m16b;
reg full, empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 5'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = m16b ? (wp + 5'h1) : (wp + 5'h2);
always @(posedge clk)
if(!en) rp <= #1 4'h0;
else
if(re) rp <= #1 rp + 4'h1;
always @(posedge clk)
status <= #1 ((rp[2:1] - wp[3:2]) - 2'h1);
always @(posedge clk)
empty <= #1 (wp[4:1] == rp[3:0]) & (m16b ? !wp[0] : 1'b0);
always @(posedge clk)
full <= #1 (wp[3:1] == rp[2:0]) & (wp[4] != rp[3]);
// Fifo Output
always @(posedge clk)
dout <= #1 mem[ rp[2:0] ];
// Fifo Input Half Word Latch
always @(posedge clk)
if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
always @(mode or din_tmp1 or din)
case(mode) // synopsys parallel_case full_case
2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output
2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
endcase
always @(posedge clk)
if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[3:1] ] <= #1 din_tmp;
endmodule
`endif
`ifdef AC97_IN_FIFO_DEPTH_16
// 16 entry deep verion of the input FIFO
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [19:0] din;
input we;
output [31:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:15];
reg [31:0] dout;
reg [5:0] wp;
reg [4:0] rp;
wire [5:0] wp_p1;
reg [1:0] status;
reg [15:0] din_tmp1;
reg [31:0] din_tmp;
wire m16b;
reg full, empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 6'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = m16b ? (wp + 6'h1) : (wp + 6'h2);
always @(posedge clk)
if(!en) rp <= #1 5'h0;
else
if(re) rp <= #1 rp + 5'h1;
always @(posedge clk)
status <= #1 ((rp[3:2] - wp[4:3]) - 2'h1);
always @(posedge clk)
empty <= #1 (wp[5:1] == rp[4:0]) & (m16b ? !wp[0] : 1'b0);
always @(posedge clk)
full <= #1 (wp[4:1] == rp[3:0]) & (wp[5] != rp[4]);
// Fifo Output
always @(posedge clk)
dout <= #1 mem[ rp[3:0] ];
// Fifo Input Half Word Latch
always @(posedge clk)
if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
always @(mode or din_tmp1 or din)
case(mode) // synopsys parallel_case full_case
2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output
2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
endcase
always @(posedge clk)
if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[4:1] ] <= #1 din_tmp;
endmodule
`endif
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Output FIFO ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_out_fifo.v,v 1.4 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_out_fifo.v,v $
// Revision 1.4 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.3 2002/03/11 03:21:22 rudi
//
// - Added defines to select fifo depth between 4, 8 and 16 entries.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:16 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
`ifdef AC97_OUT_FIFO_DEPTH_4
// 4 Entry Deep version of the Output FIFO
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:3];
reg [2:0] wp;
reg [3:0] rp;
wire [2:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 3'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 3'h1;
always @(posedge clk)
if(!en) rp <= #1 4'h0;
else
if(re & m16b) rp <= #1 rp + 4'h1;
else
if(re & !m16b) rp <= #1 rp + 4'h2;
always @(posedge clk)
status <= #1 (wp[1:0] - rp[2:1]) - 2'h1;
wire [3:0] rp_p1 = rp[3:0] + 4'h1;
always @(posedge clk)
empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]);
// Fifo Output
assign dout_tmp = mem[ rp[2:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[1:0]] <= #1 din;
endmodule
`endif
`ifdef AC97_OUT_FIFO_DEPTH_8
// 8 Entry Deep version of the Output FIFO
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:7];
reg [3:0] wp;
reg [4:0] rp;
wire [3:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 4'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 4'h1;
always @(posedge clk)
if(!en) rp <= #1 5'h0;
else
if(re & m16b) rp <= #1 rp + 5'h1;
else
if(re & !m16b) rp <= #1 rp + 5'h2;
always @(posedge clk)
status <= #1 (wp[2:1] - rp[3:2]) - 2'h1;
wire [4:0] rp_p1 = rp[4:0] + 5'h1;
always @(posedge clk)
empty <= #1 (rp_p1[4:1] == wp[3:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[2:0] == rp[3:1]) & (wp[3] != rp[4]);
// Fifo Output
assign dout_tmp = mem[ rp[3:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[2:0]] <= #1 din;
endmodule
`endif
`ifdef AC97_OUT_FIFO_DEPTH_16
// 16 Entry Deep version of the Output FIFO
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:15];
reg [4:0] wp;
reg [5:0] rp;
wire [4:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 5'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 4'h1;
always @(posedge clk)
if(!en) rp <= #1 6'h0;
else
if(re & m16b) rp <= #1 rp + 6'h1;
else
if(re & !m16b) rp <= #1 rp + 6'h2;
always @(posedge clk)
status <= #1 (wp[3:2] - rp[4:3]) - 2'h1;
wire [5:0] rp_p1 = rp[5:0] + 6'h1;
always @(posedge clk)
empty <= #1 (rp_p1[5:1] == wp[4:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[3:0] == rp[4:1]) & (wp[4] != rp[5]);
// Fifo Output
assign dout_tmp = mem[ rp[4:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[3:0]] <= #1 din;
endmodule
`endif
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// PCM Request Controller ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_prc.v,v 1.4 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_prc.v,v $
// Revision 1.4 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.3 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:17 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_prc(clk, rst,
// SR Slot Interface
valid, in_valid, out_slt0,
in_slt0, in_slt1,
// Codec Register Access
crac_valid, crac_wr,
// Channel Configuration
oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
ic0_cfg, ic1_cfg, ic2_cfg,
// FIFO Status
o3_empty, o4_empty, o6_empty, o7_empty, o8_empty,
o9_empty, i3_full, i4_full, i6_full,
// FIFO Control
o3_re, o4_re, o6_re, o7_re, o8_re, o9_re,
i3_we, i4_we, i6_we
);
input clk, rst;
input valid;
input [2:0] in_valid;
output [15:0] out_slt0;
input [15:0] in_slt0;
input [19:0] in_slt1;
input crac_valid;
input crac_wr;
input [7:0] oc0_cfg;
input [7:0] oc1_cfg;
input [7:0] oc2_cfg;
input [7:0] oc3_cfg;
input [7:0] oc4_cfg;
input [7:0] oc5_cfg;
input [7:0] ic0_cfg;
input [7:0] ic1_cfg;
input [7:0] ic2_cfg;
input o3_empty;
input o4_empty;
input o6_empty;
input o7_empty;
input o8_empty;
input o9_empty;
input i3_full;
input i4_full;
input i6_full;
output o3_re;
output o4_re;
output o6_re;
output o7_re;
output o8_re;
output o9_re;
output i3_we;
output i4_we;
output i6_we;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire o3_re_l;
wire o4_re_l;
wire o6_re_l;
wire o7_re_l;
wire o8_re_l;
wire o9_re_l;
reg crac_valid_r;
reg crac_wr_r;
////////////////////////////////////////////////////////////////////
//
// Output Tag Assembly
//
assign out_slt0[15] = |out_slt0[14:6];
assign out_slt0[14] = crac_valid_r;
assign out_slt0[13] = crac_wr_r;
assign out_slt0[12] = o3_re_l;
assign out_slt0[11] = o4_re_l;
assign out_slt0[10] = 1'b0;
assign out_slt0[09] = o6_re_l;
assign out_slt0[08] = o7_re_l;
assign out_slt0[07] = o8_re_l;
assign out_slt0[06] = o9_re_l;
assign out_slt0[5:0] = 6'h0;
////////////////////////////////////////////////////////////////////
//
// FIFO Control
//
always @(posedge clk)
if(valid) crac_valid_r <= #1 crac_valid;
always @(posedge clk)
if(valid) crac_wr_r <= #1 crac_valid & crac_wr;
// Output Channel 0 (Out Slot 3)
ac97_fifo_ctrl u0(
.clk( clk ),
.valid( valid ),
.ch_en( oc0_cfg[0] ),
.srs( oc0_cfg[1] ),
.full_empty( o3_empty ),
.req( ~in_slt1[11] ),
.crdy( in_slt0[15] ),
.en_out( o3_re ),
.en_out_l( o3_re_l )
);
// Output Channel 1 (Out Slot 4)
ac97_fifo_ctrl u1(
.clk( clk ),
.valid( valid ),
.ch_en( oc1_cfg[0] ),
.srs( oc1_cfg[1] ),
.full_empty( o4_empty ),
.req( ~in_slt1[10] ),
.crdy( in_slt0[15] ),
.en_out( o4_re ),
.en_out_l( o4_re_l )
);
`ifdef AC97_CENTER
// Output Channel 2 (Out Slot 6)
ac97_fifo_ctrl u2(
.clk( clk ),
.valid( valid ),
.ch_en( oc2_cfg[0] ),
.srs( oc2_cfg[1] ),
.full_empty( o6_empty ),
.req( ~in_slt1[8] ),
.crdy( in_slt0[15] ),
.en_out( o6_re ),
.en_out_l( o6_re_l )
);
`else
assign o6_re = 1'b0;
assign o6_re_l = 1'b0;
`endif
`ifdef AC97_SURROUND
// Output Channel 3 (Out Slot 7)
ac97_fifo_ctrl u3(
.clk( clk ),
.valid( valid ),
.ch_en( oc3_cfg[0] ),
.srs( oc3_cfg[1] ),
.full_empty( o7_empty ),
.req( ~in_slt1[7] ),
.crdy( in_slt0[15] ),
.en_out( o7_re ),
.en_out_l( o7_re_l )
);
// Output Channel 4 (Out Slot 8)
ac97_fifo_ctrl u4(
.clk( clk ),
.valid( valid ),
.ch_en( oc4_cfg[0] ),
.srs( oc4_cfg[1] ),
.full_empty( o8_empty ),
.req( ~in_slt1[6] ),
.crdy( in_slt0[15] ),
.en_out( o8_re ),
.en_out_l( o8_re_l )
);
`else
assign o7_re = 1'b0;
assign o7_re_l = 1'b0;
assign o8_re = 1'b0;
assign o8_re_l = 1'b0;
`endif
`ifdef AC97_LFE
// Output Channel 5 (Out Slot 9)
ac97_fifo_ctrl u5(
.clk( clk ),
.valid( valid ),
.ch_en( oc5_cfg[0] ),
.srs( oc5_cfg[1] ),
.full_empty( o9_empty ),
.req( ~in_slt1[5] ),
.crdy( in_slt0[15] ),
.en_out( o9_re ),
.en_out_l( o9_re_l )
);
`else
assign o9_re = 1'b0;
assign o9_re_l = 1'b0;
`endif
`ifdef AC97_SIN
// Input Channel 0 (In Slot 3)
ac97_fifo_ctrl u6(
.clk( clk ),
.valid( in_valid[0] ),
.ch_en( ic0_cfg[0] ),
.srs( ic0_cfg[1] ),
.full_empty( i3_full ),
.req( in_slt0[12] ),
.crdy( in_slt0[15] ),
.en_out( i3_we ),
.en_out_l( )
);
// Input Channel 1 (In Slot 4)
ac97_fifo_ctrl u7(
.clk( clk ),
.valid( in_valid[1] ),
.ch_en( ic1_cfg[0] ),
.srs( ic1_cfg[1] ),
.full_empty( i4_full ),
.req( in_slt0[11] ),
.crdy( in_slt0[15] ),
.en_out( i4_we ),
.en_out_l( )
);
`else
assign i3_we = 1'b0;
assign i4_we = 1'b0;
`endif
`ifdef AC97_MICIN
// Input Channel 2 (In Slot 6)
ac97_fifo_ctrl u8(
.clk( clk ),
.valid( in_valid[2] ),
.ch_en( ic2_cfg[0] ),
.srs( ic2_cfg[1] ),
.full_empty( i6_full ),
.req( in_slt0[9] ),
.crdy( in_slt0[15] ),
.en_out( i6_we ),
.en_out_l( )
);
`else
assign i6_we = 1'b0;
`endif
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Register File ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_rf.v,v 1.4 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_rf.v,v $
// Revision 1.4 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.3 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:17 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_rf(clk, rst,
adr, rf_dout, rf_din,
rf_we, rf_re, int, ac97_rst_force,
resume_req, suspended,
crac_we, crac_din, crac_out,
crac_rd_done, crac_wr_done,
oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
ic0_cfg, ic1_cfg, ic2_cfg,
oc0_int_set, oc1_int_set, oc2_int_set, oc3_int_set,
oc4_int_set, oc5_int_set,
ic0_int_set, ic1_int_set, ic2_int_set
);
input clk,rst;
input [3:0] adr;
output [31:0] rf_dout;
input [31:0] rf_din;
input rf_we;
input rf_re;
output int;
output ac97_rst_force;
output resume_req;
input suspended;
output crac_we;
input [15:0] crac_din;
output [31:0] crac_out;
input crac_rd_done, crac_wr_done;
output [7:0] oc0_cfg;
output [7:0] oc1_cfg;
output [7:0] oc2_cfg;
output [7:0] oc3_cfg;
output [7:0] oc4_cfg;
output [7:0] oc5_cfg;
output [7:0] ic0_cfg;
output [7:0] ic1_cfg;
output [7:0] ic2_cfg;
input [2:0] oc0_int_set;
input [2:0] oc1_int_set;
input [2:0] oc2_int_set;
input [2:0] oc3_int_set;
input [2:0] oc4_int_set;
input [2:0] oc5_int_set;
input [2:0] ic0_int_set;
input [2:0] ic1_int_set;
input [2:0] ic2_int_set;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] rf_dout;
reg [31:0] csr_r;
reg [31:0] occ0_r;
reg [15:0] occ1_r;
reg [23:0] icc_r;
reg [31:0] crac_r;
reg [28:0] intm_r;
reg [28:0] ints_r;
reg int;
wire [28:0] int_all;
wire [31:0] csr, occ0, occ1, icc, crac, intm, ints;
reg [15:0] crac_dout_r;
reg ac97_rst_force;
reg resume_req;
// Aliases
assign csr = {30'h0, suspended, 1'h0};
assign occ0 = occ0_r;
assign occ1 = {16'h0, occ1_r};
assign icc = {8'h0, icc_r};
assign crac = {crac_r[7], 8'h0, crac_r[6:0], crac_din};
assign intm = {3'h0, intm_r};
assign ints = {3'h0, ints_r};
assign crac_out = {crac_r[7], 8'h0, crac_r[6:0], crac_dout_r};
////////////////////////////////////////////////////////////////////
//
// Register WISHBONE Interface
//
always @(adr or csr or occ0 or occ1 or icc or crac or intm or ints)
case(adr[2:0]) // synopsys parallel_case full_case
0: rf_dout = csr;
1: rf_dout = occ0;
2: rf_dout = occ1;
3: rf_dout = icc;
4: rf_dout = crac;
5: rf_dout = intm;
6: rf_dout = ints;
endcase
always @(posedge clk or negedge rst)
if(!rst) csr_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==3'h0)) csr_r <= #1 rf_din;
always @(posedge clk)
if(rf_we & (adr[2:0]==3'h0)) ac97_rst_force <= #1 rf_din[0];
else ac97_rst_force <= #1 1'b0;
always @(posedge clk)
if(rf_we & (adr[2:0]==3'h0)) resume_req <= #1 rf_din[1];
else resume_req <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) occ0_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==3'h1)) occ0_r <= #1 rf_din;
always @(posedge clk or negedge rst)
if(!rst) occ1_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==3'h2)) occ1_r <= #1 rf_din[23:0];
always @(posedge clk or negedge rst)
if(!rst) icc_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==3'h3)) icc_r <= #1 rf_din[23:0];
assign crac_we = rf_we & (adr[2:0]==3'h4);
always @(posedge clk or negedge rst)
if(!rst) crac_r <= #1 1'b0;
else
if(crac_we) crac_r <= #1 {rf_din[31], rf_din[22:16]};
always @(posedge clk)
if(crac_we) crac_dout_r <= #1 rf_din[15:0];
always @(posedge clk or negedge rst)
if(!rst) intm_r <= #1 1'b0;
else
if(rf_we & (adr[2:0]==3'h5)) intm_r <= #1 rf_din[28:0];
// Interrupt Source Register
always @(posedge clk or negedge rst)
if(!rst) ints_r <= #1 1'b0;
else
if(rf_re & (adr[2:0]==3'h6)) ints_r <= #1 1'b0;
else
begin
if(crac_rd_done) ints_r[0] <= #1 1'b1;
if(crac_wr_done) ints_r[1] <= #1 1'b1;
if(oc0_int_set[0]) ints_r[2] <= #1 1'b1;
if(oc0_int_set[1]) ints_r[3] <= #1 1'b1;
if(oc0_int_set[2]) ints_r[4] <= #1 1'b1;
if(oc1_int_set[0]) ints_r[5] <= #1 1'b1;
if(oc1_int_set[1]) ints_r[6] <= #1 1'b1;
if(oc1_int_set[2]) ints_r[7] <= #1 1'b1;
`ifdef AC97_CENTER
if(oc2_int_set[0]) ints_r[8] <= #1 1'b1;
if(oc2_int_set[1]) ints_r[9] <= #1 1'b1;
if(oc2_int_set[2]) ints_r[10] <= #1 1'b1;
`endif
`ifdef AC97_SURROUND
if(oc3_int_set[0]) ints_r[11] <= #1 1'b1;
if(oc3_int_set[1]) ints_r[12] <= #1 1'b1;
if(oc3_int_set[2]) ints_r[13] <= #1 1'b1;
if(oc4_int_set[0]) ints_r[14] <= #1 1'b1;
if(oc4_int_set[1]) ints_r[15] <= #1 1'b1;
if(oc4_int_set[2]) ints_r[16] <= #1 1'b1;
`endif
`ifdef AC97_LFE
if(oc5_int_set[0]) ints_r[17] <= #1 1'b1;
if(oc5_int_set[1]) ints_r[18] <= #1 1'b1;
if(oc5_int_set[2]) ints_r[19] <= #1 1'b1;
`endif
`ifdef AC97_SIN
if(ic0_int_set[0]) ints_r[20] <= #1 1'b1;
if(ic0_int_set[1]) ints_r[21] <= #1 1'b1;
if(ic0_int_set[2]) ints_r[22] <= #1 1'b1;
if(ic1_int_set[0]) ints_r[23] <= #1 1'b1;
if(ic1_int_set[1]) ints_r[24] <= #1 1'b1;
if(ic1_int_set[2]) ints_r[25] <= #1 1'b1;
`endif
`ifdef AC97_MICIN
if(ic2_int_set[0]) ints_r[26] <= #1 1'b1;
if(ic2_int_set[1]) ints_r[27] <= #1 1'b1;
if(ic2_int_set[2]) ints_r[28] <= #1 1'b1;
`endif
end
////////////////////////////////////////////////////////////////////
//
// Register Internal Interface
//
assign oc0_cfg = occ0[7:0];
assign oc1_cfg = occ0[15:8];
assign oc2_cfg = occ0[23:16];
assign oc3_cfg = occ0[31:24];
assign oc4_cfg = occ1[7:0];
assign oc5_cfg = occ1[15:8];
assign ic0_cfg = icc[7:0];
assign ic1_cfg = icc[15:8];
assign ic2_cfg = icc[23:16];
////////////////////////////////////////////////////////////////////
//
// Interrupt Generation
//
assign int_all = intm_r & ints_r;
always @(posedge clk)
int <= #1 |int_all;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller Reset Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_rst.v,v 1.1 2001/08/03 06:54:50 rudi Exp $
//
// $Date: 2001/08/03 06:54:50 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_rst.v,v $
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:19 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_rst(clk, rst, rst_force, ps_ce, ac97_rst_);
input clk, rst;
input rst_force;
output ps_ce;
output ac97_rst_;
reg ac97_rst_;
reg [2:0] cnt;
wire ce;
wire to;
reg [5:0] ps_cnt;
wire ps_ce;
always @(posedge clk or negedge rst)
if(!rst) ac97_rst_ <= #1 0;
else
if(rst_force) ac97_rst_ <= #1 0;
else
if(to) ac97_rst_ <= #1 1;
assign to = (cnt == `AC97_RST_DEL);
always @(posedge clk or negedge rst)
if(!rst) cnt <= #1 0;
else
if(rst_force) cnt <= #1 0;
else
if(ce) cnt <= #1 cnt + 1;
assign ce = ps_ce & (cnt != `AC97_RST_DEL);
always @(posedge clk or negedge rst)
if(!rst) ps_cnt <= #1 0;
else
if(ps_ce | rst_force) ps_cnt <= #1 0;
else ps_cnt <= #1 ps_cnt + 1;
assign ps_ce = (ps_cnt == `AC97_250_PS);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Serial Input Block ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_sin.v,v 1.2 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_sin.v,v $
// Revision 1.2 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_sin(clk, rst,
out_le, slt0, slt1, slt2, slt3, slt4,
slt6,
sdata_in
);
input clk, rst;
// --------------------------------------
// Misc Signals
input [5:0] out_le;
output [15:0] slt0;
output [19:0] slt1;
output [19:0] slt2;
output [19:0] slt3;
output [19:0] slt4;
output [19:0] slt6;
// --------------------------------------
// AC97 Codec Interface
input sdata_in;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg sdata_in_r;
reg [19:0] sr;
reg [15:0] slt0;
reg [19:0] slt1;
reg [19:0] slt2;
reg [19:0] slt3;
reg [19:0] slt4;
reg [19:0] slt6;
////////////////////////////////////////////////////////////////////
//
// Output Registers
//
always @(posedge clk)
if(out_le[0]) slt0 <= #1 sr[15:0];
always @(posedge clk)
if(out_le[1]) slt1 <= #1 sr;
always @(posedge clk)
if(out_le[2]) slt2 <= #1 sr;
always @(posedge clk)
if(out_le[3]) slt3 <= #1 sr;
always @(posedge clk)
if(out_le[4]) slt4 <= #1 sr;
always @(posedge clk)
if(out_le[5]) slt6 <= #1 sr;
////////////////////////////////////////////////////////////////////
//
// Serial Shift Register
//
always @(negedge clk)
sdata_in_r <= #1 sdata_in;
always @(posedge clk)
sr <= #1 {sr[18:0], sdata_in_r };
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Serial Output Controller ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_soc.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_soc.v,v $
// Revision 1.3 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_soc(clk, wclk, rst,
ps_ce, resume, suspended,
sync, out_le, in_valid, ld, valid
);
input clk, wclk, rst;
input ps_ce;
input resume;
output suspended;
output sync;
output [5:0] out_le;
output [2:0] in_valid;
output ld;
output valid;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [7:0] cnt;
reg sync_beat;
reg sync_resume;
reg [5:0] out_le;
reg ld;
reg valid;
reg [2:0] in_valid;
reg bit_clk_r;
reg bit_clk_r1;
reg bit_clk_e;
reg suspended;
wire to;
reg [5:0] to_cnt;
reg [3:0] res_cnt;
wire resume_done;
assign sync = sync_beat | sync_resume;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or negedge rst)
if(!rst) cnt <= #1 8'hff;
else
if(suspended) cnt <= #1 8'hff;
else cnt <= #1 cnt + 8'h1;
always @(posedge clk)
ld <= #1 (cnt == 8'h00);
always @(posedge clk)
sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
always @(posedge clk)
valid <= #1 (cnt > 8'h39);
always @(posedge clk)
out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable
always @(posedge clk)
out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable
always @(posedge clk)
out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable
always @(posedge clk)
out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable
always @(posedge clk)
out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable
always @(posedge clk)
out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable
always @(posedge clk)
in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
always @(posedge clk)
in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid
always @(posedge clk)
in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid
////////////////////////////////////////////////////////////////////
//
// Suspend Detect
//
always @(posedge wclk)
bit_clk_r <= #1 clk;
always @(posedge wclk)
bit_clk_r1 <= #1 bit_clk_r;
always @(posedge wclk)
bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1);
always @(posedge wclk)
suspended <= #1 to;
assign to = (to_cnt == `AC97_SUSP_DET);
always @(posedge wclk or negedge rst)
if(!rst) to_cnt <= #1 6'h0;
else
if(bit_clk_e) to_cnt <= #1 6'h0;
else
if(!to) to_cnt <= #1 to_cnt + 6'h1;
////////////////////////////////////////////////////////////////////
//
// Resume Signaling
//
always @(posedge wclk or negedge rst)
if(!rst) sync_resume <= #1 1'b0;
else
if(resume_done) sync_resume <= #1 1'b0;
else
if(suspended & resume) sync_resume <= #1 1'b1;
assign resume_done = (res_cnt == `AC97_RES_SIG);
always @(posedge wclk)
if(!sync_resume) res_cnt <= #1 4'h0;
else
if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Serial Output Block ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_sout.v,v 1.2 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_sout.v,v $
// Revision 1.2 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_sout(clk, rst,
so_ld, slt0, slt1, slt2, slt3, slt4,
slt6, slt7, slt8, slt9,
sdata_out
);
input clk, rst;
// --------------------------------------
// Misc Signals
input so_ld;
input [15:0] slt0;
input [19:0] slt1;
input [19:0] slt2;
input [19:0] slt3;
input [19:0] slt4;
input [19:0] slt6;
input [19:0] slt7;
input [19:0] slt8;
input [19:0] slt9;
// --------------------------------------
// AC97 Codec Interface
output sdata_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire sdata_out;
reg [15:0] slt0_r;
reg [19:0] slt1_r;
reg [19:0] slt2_r;
reg [19:0] slt3_r;
reg [19:0] slt4_r;
reg [19:0] slt5_r;
reg [19:0] slt6_r;
reg [19:0] slt7_r;
reg [19:0] slt8_r;
reg [19:0] slt9_r;
reg [19:0] slt10_r;
reg [19:0] slt11_r;
reg [19:0] slt12_r;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
////////////////////////////////////////////////////////////////////
//
// Serial Shift Register
//
assign sdata_out = slt0_r[15];
always @(posedge clk)
if(so_ld) slt0_r <= #1 slt0;
else slt0_r <= #1 {slt0_r[14:0], slt1_r[19]};
always @(posedge clk)
if(so_ld) slt1_r <= #1 slt1;
else slt1_r <= #1 {slt1_r[18:0], slt2_r[19]};
always @(posedge clk)
if(so_ld) slt2_r <= #1 slt2;
else slt2_r <= #1 {slt2_r[18:0], slt3_r[19]};
always @(posedge clk)
if(so_ld) slt3_r <= #1 slt3;
else slt3_r <= #1 {slt3_r[18:0], slt4_r[19]};
always @(posedge clk)
if(so_ld) slt4_r <= #1 slt4;
else slt4_r <= #1 {slt4_r[18:0], slt5_r[19]};
always @(posedge clk)
if(so_ld) slt5_r <= #1 20'h0;
else slt5_r <= #1 {slt5_r[18:0], slt6_r[19]};
always @(posedge clk)
if(so_ld) slt6_r <= #1 slt6;
else slt6_r <= #1 {slt6_r[18:0], slt7_r[19]};
always @(posedge clk)
if(so_ld) slt7_r <= #1 slt7;
else slt7_r <= #1 {slt7_r[18:0], slt8_r[19]};
always @(posedge clk)
if(so_ld) slt8_r <= #1 slt8;
else slt8_r <= #1 {slt8_r[18:0], slt9_r[19]};
always @(posedge clk)
if(so_ld) slt9_r <= #1 slt9;
else slt9_r <= #1 {slt9_r[18:0], slt10_r[19]};
always @(posedge clk)
if(so_ld) slt10_r <= #1 20'h0;
else slt10_r <= #1 {slt10_r[18:0], slt11_r[19]};
always @(posedge clk)
if(so_ld) slt11_r <= #1 20'h0;
else slt11_r <= #1 {slt11_r[18:0], slt12_r[19]};
always @(posedge clk)
if(so_ld) slt12_r <= #1 20'h0;
else slt12_r <= #1 {slt12_r[18:0], 1'b0 };
endmodule
|
`include "ac97_defines.v"
module ac97_top(
clk,
rst_i,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
int_o, dma_req_o, dma_ack_i,
suspended_o,
sync_pad_o, sdata_pad_o, sdata_pad_i,
ac97_reset_pad_o_
);
input clk, rst_i;
// --------------------------------------
// WISHBONE SLAVE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
// --------------------------------------
// Misc Signals
output int_o;
output [8:0] dma_req_o;
input [8:0] dma_ack_i;
// --------------------------------------
// Suspend Resume Interface
output suspended_o;
// --------------------------------------
// AC97 Codec Interface
output sync_pad_o;
output sdata_pad_o;
input sdata_pad_i;
output ac97_reset_pad_o_;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire bit_clk_pad_i = clk;
// Serial Output register interface
wire [15:0] out_slt0;
wire [19:0] out_slt1;
wire [19:0] out_slt2;
wire [19:0] out_slt3;
wire [19:0] out_slt4;
wire [19:0] out_slt6;
wire [19:0] out_slt7;
wire [19:0] out_slt8;
wire [19:0] out_slt9;
// Serial Input register interface
wire [15:0] in_slt0;
wire [19:0] in_slt1;
wire [19:0] in_slt2;
wire [19:0] in_slt3;
wire [19:0] in_slt4;
wire [19:0] in_slt6;
// Serial IO Controller Interface
wire ld;
wire valid;
wire [5:0] out_le;
wire [2:0] in_valid;
wire ps_ce;
// Valid Sync
reg valid_s1, valid_s;
reg [2:0] in_valid_s1, in_valid_s;
// Out FIFO interface
wire [31:0] wb_din;
wire [1:0] o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode;
wire o3_re, o4_re, o6_re, o7_re, o8_re, o9_re;
wire o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
wire [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;
wire o3_full, o4_full, o6_full, o7_full, o8_full, o9_full;
wire o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;
// In FIFO interface
wire [31:0] i3_dout, i4_dout, i6_dout;
wire [1:0] i3_mode, i4_mode, i6_mode;
wire i3_we, i4_we, i6_we;
wire i3_re, i4_re, i6_re;
wire [1:0] i3_status, i4_status, i6_status;
wire i3_full, i4_full, i6_full;
wire i3_empty, i4_empty, i6_empty;
// Register File Interface
wire [3:0] adr;
wire [31:0] rf_dout;
wire [31:0] rf_din;
wire rf_we;
wire rf_re;
wire ac97_rst_force;
wire resume_req;
wire crac_we;
wire [15:0] crac_din;
wire [31:0] crac_out;
wire [7:0] oc0_cfg;
wire [7:0] oc1_cfg;
wire [7:0] oc2_cfg;
wire [7:0] oc3_cfg;
wire [7:0] oc4_cfg;
wire [7:0] oc5_cfg;
wire [7:0] ic0_cfg;
wire [7:0] ic1_cfg;
wire [7:0] ic2_cfg;
wire [2:0] oc0_int_set;
wire [2:0] oc1_int_set;
wire [2:0] oc2_int_set;
wire [2:0] oc3_int_set;
wire [2:0] oc4_int_set;
wire [2:0] oc5_int_set;
wire [2:0] ic0_int_set;
wire [2:0] ic1_int_set;
wire [2:0] ic2_int_set;
// CRA Module interface
wire crac_valid;
wire crac_wr;
wire crac_wr_done, crac_rd_done;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
// Sync Valid to WISHBONE Clock
always @(posedge clk)
valid_s1 <= #1 valid;
always @(posedge clk)
valid_s <= #1 valid_s1;
always @(posedge clk)
in_valid_s1 <= #1 in_valid;
always @(posedge clk)
in_valid_s <= #1 in_valid_s1;
// "valid_s" Indicates when any of the outputs to the output S/R may
// change or when outputs from input S/R may be sampled
assign o3_mode = oc0_cfg[3:2];
assign o4_mode = oc1_cfg[3:2];
assign o6_mode = oc2_cfg[3:2];
assign o7_mode = oc3_cfg[3:2];
assign o8_mode = oc4_cfg[3:2];
assign o9_mode = oc5_cfg[3:2];
assign i3_mode = ic0_cfg[3:2];
assign i4_mode = ic1_cfg[3:2];
assign i6_mode = ic2_cfg[3:2];
////////////////////////////////////////////////////////////////////
//
// Modules
//
ac97_sout u0(
.clk( bit_clk_pad_i ),
.rst( rst_i ),
.so_ld( ld ),
.slt0( out_slt0 ),
.slt1( out_slt1 ),
.slt2( out_slt2 ),
.slt3( out_slt3 ),
.slt4( out_slt4 ),
.slt6( out_slt6 ),
.slt7( out_slt7 ),
.slt8( out_slt8 ),
.slt9( out_slt9 ),
.sdata_out( sdata_pad_o )
);
ac97_sin u1(
.clk( bit_clk_pad_i ),
.rst( rst_i ),
.out_le( out_le ),
.slt0( in_slt0 ),
.slt1( in_slt1 ),
.slt2( in_slt2 ),
.slt3( in_slt3 ),
.slt4( in_slt4 ),
.slt6( in_slt6 ),
.sdata_in( sdata_pad_i )
);
ac97_soc u2(
.clk( bit_clk_pad_i ),
.wclk( clk ),
.rst( rst_i ),
.ps_ce( ps_ce ),
.resume( resume_req ),
.suspended( suspended_o ),
.sync( sync_pad_o ),
.out_le( out_le ),
.in_valid( in_valid ),
.ld( ld ),
.valid( valid )
);
ac97_out_fifo u3(
.clk( clk ),
.rst( rst_i ),
.en( oc0_cfg[0] ),
.mode( o3_mode ),
.din( wb_din ),
.we( o3_we ),
.dout( out_slt3 ),
.re( o3_re ),
.status( o3_status ),
.full( o3_full ),
.empty( o3_empty )
);
ac97_out_fifo u4(
.clk( clk ),
.rst( rst_i ),
.en( oc1_cfg[0] ),
.mode( o4_mode ),
.din( wb_din ),
.we( o4_we ),
.dout( out_slt4 ),
.re( o4_re ),
.status( o4_status ),
.full( o4_full ),
.empty( o4_empty )
);
`ifdef AC97_CENTER
ac97_out_fifo u5(
.clk( clk ),
.rst( rst_i ),
.en( oc2_cfg[0] ),
.mode( o6_mode ),
.din( wb_din ),
.we( o6_we ),
.dout( out_slt6 ),
.re( o6_re ),
.status( o6_status ),
.full( o6_full ),
.empty( o6_empty )
);
`else
assign out_slt6 = 20'h0;
assign o6_status = 2'h0;
assign o6_full = 1'b0;
assign o6_empty = 1'b0;
`endif
`ifdef AC97_SURROUND
ac97_out_fifo u6(
.clk( clk ),
.rst( rst_i ),
.en( oc3_cfg[0] ),
.mode( o7_mode ),
.din( wb_din ),
.we( o7_we ),
.dout( out_slt7 ),
.re( o7_re ),
.status( o7_status ),
.full( o7_full ),
.empty( o7_empty )
);
ac97_out_fifo u7(
.clk( clk ),
.rst( rst_i ),
.en( oc4_cfg[0] ),
.mode( o8_mode ),
.din( wb_din ),
.we( o8_we ),
.dout( out_slt8 ),
.re( o8_re ),
.status( o8_status ),
.full( o8_full ),
.empty( o8_empty )
);
`else
assign out_slt7 = 20'h0;
assign o7_status = 2'h0;
assign o7_full = 1'b0;
assign o7_empty = 1'b0;
assign out_slt8 = 20'h0;
assign o8_status = 2'h0;
assign o8_full = 1'b0;
assign o8_empty = 1'b0;
`endif
`ifdef AC97_LFE
ac97_out_fifo u8(
.clk( clk ),
.rst( rst_i ),
.en( oc5_cfg[0] ),
.mode( o9_mode ),
.din( wb_din ),
.we( o9_we ),
.dout( out_slt9 ),
.re( o9_re ),
.status( o9_status ),
.full( o9_full ),
.empty( o9_empty )
);
`else
assign out_slt9 = 20'h0;
assign o9_status = 2'h0;
assign o9_full = 1'b0;
assign o9_empty = 1'b0;
`endif
`ifdef AC97_SIN
ac97_in_fifo u9(
.clk( clk ),
.rst( rst_i ),
.en( ic0_cfg[0] ),
.mode( i3_mode ),
.din( in_slt3 ),
.we( i3_we ),
.dout( i3_dout ),
.re( i3_re ),
.status( i3_status ),
.full( i3_full ),
.empty( i3_empty )
);
ac97_in_fifo u10(
.clk( clk ),
.rst( rst_i ),
.en( ic1_cfg[0] ),
.mode( i4_mode ),
.din( in_slt4 ),
.we( i4_we ),
.dout( i4_dout ),
.re( i4_re ),
.status( i4_status ),
.full( i4_full ),
.empty( i4_empty )
);
`else
assign i3_dout = 20'h0;
assign i3_status = 2'h0;
assign i3_full = 1'b0;
assign i3_empty = 1'b0;
assign i4_dout = 20'h0;
assign i4_status = 2'h0;
assign i4_full = 1'b0;
assign i4_empty = 1'b0;
`endif
`ifdef AC97_MICIN
ac97_in_fifo u11(
.clk( clk ),
.rst( rst_i ),
.en( ic2_cfg[0] ),
.mode( i6_mode ),
.din( in_slt6 ),
.we( i6_we ),
.dout( i6_dout ),
.re( i6_re ),
.status( i6_status ),
.full( i6_full ),
.empty( i6_empty )
);
`else
assign i6_dout = 20'h0;
assign i6_status = 2'h0;
assign i6_full = 1'b0;
assign i6_empty = 1'b0;
`endif
ac97_wb_if u12(
.clk( clk ),
.rst( rst_i ),
.wb_data_i( wb_data_i ),
.wb_data_o( wb_data_o ),
.wb_addr_i( wb_addr_i ),
.wb_sel_i( wb_sel_i ),
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( wb_ack_o ),
.wb_err_o( wb_err_o ),
.adr( adr ),
.dout( wb_din ),
.rf_din( rf_dout ),
.i3_din( i3_dout ),
.i4_din( i4_dout ),
.i6_din( i6_dout ),
.rf_we( rf_we ),
.rf_re( rf_re ),
.o3_we( o3_we ),
.o4_we( o4_we ),
.o6_we( o6_we ),
.o7_we( o7_we ),
.o8_we( o8_we ),
.o9_we( o9_we ),
.i3_re( i3_re ),
.i4_re( i4_re ),
.i6_re( i6_re )
);
ac97_rf u13( .clk( clk ),
.rst( rst_i ),
.adr( adr ),
.rf_dout( rf_dout ),
.rf_din( wb_din ),
.rf_we( rf_we ),
.rf_re( rf_re ),
.int( int_o ),
.ac97_rst_force(ac97_rst_force ),
.resume_req( resume_req ),
.suspended( suspended_o ),
.crac_we( crac_we ),
.crac_din( crac_din ),
.crac_out( crac_out ),
.crac_wr_done( crac_wr_done ),
.crac_rd_done( crac_rd_done ),
.oc0_cfg( oc0_cfg ),
.oc1_cfg( oc1_cfg ),
.oc2_cfg( oc2_cfg ),
.oc3_cfg( oc3_cfg ),
.oc4_cfg( oc4_cfg ),
.oc5_cfg( oc5_cfg ),
.ic0_cfg( ic0_cfg ),
.ic1_cfg( ic1_cfg ),
.ic2_cfg( ic2_cfg ),
.oc0_int_set( oc0_int_set ),
.oc1_int_set( oc1_int_set ),
.oc2_int_set( oc2_int_set ),
.oc3_int_set( oc3_int_set ),
.oc4_int_set( oc4_int_set ),
.oc5_int_set( oc5_int_set ),
.ic0_int_set( ic0_int_set ),
.ic1_int_set( ic1_int_set ),
.ic2_int_set( ic2_int_set )
);
ac97_prc u14( .clk( clk ),
.rst( rst_i ),
.valid( valid_s ),
.in_valid( in_valid_s ),
.out_slt0( out_slt0 ),
.in_slt0( in_slt0 ),
.in_slt1( in_slt1 ),
.crac_valid( crac_valid ),
.crac_wr( crac_wr ),
.oc0_cfg( oc0_cfg ),
.oc1_cfg( oc1_cfg ),
.oc2_cfg( oc2_cfg ),
.oc3_cfg( oc3_cfg ),
.oc4_cfg( oc4_cfg ),
.oc5_cfg( oc5_cfg ),
.ic0_cfg( ic0_cfg ),
.ic1_cfg( ic1_cfg ),
.ic2_cfg( ic2_cfg ),
.o3_empty( o3_empty ),
.o4_empty( o4_empty ),
.o6_empty( o6_empty ),
.o7_empty( o7_empty ),
.o8_empty( o8_empty ),
.o9_empty( o9_empty ),
.i3_full( i3_full ),
.i4_full( i4_full ),
.i6_full( i6_full ),
.o3_re( o3_re ),
.o4_re( o4_re ),
.o6_re( o6_re ),
.o7_re( o7_re ),
.o8_re( o8_re ),
.o9_re( o9_re ),
.i3_we( i3_we ),
.i4_we( i4_we ),
.i6_we( i6_we )
);
ac97_cra u15( .clk( clk ),
.rst( rst_i ),
.crac_we( crac_we ),
.crac_din( crac_din ),
.crac_out( crac_out ),
.crac_wr_done( crac_wr_done ),
.crac_rd_done( crac_rd_done ),
.valid( valid_s ),
.out_slt1( out_slt1 ),
.out_slt2( out_slt2 ),
.in_slt2( in_slt2 ),
.crac_valid( crac_valid ),
.crac_wr( crac_wr )
);
ac97_dma_if u16(.clk( clk ),
.rst( rst_i ),
.o3_status( o3_status ),
.o4_status( o4_status ),
.o6_status( o6_status ),
.o7_status( o7_status ),
.o8_status( o8_status ),
.o9_status( o9_status ),
.o3_empty( o3_empty ),
.o4_empty( o4_empty ),
.o6_empty( o6_empty ),
.o7_empty( o7_empty ),
.o8_empty( o8_empty ),
.o9_empty( o9_empty ),
.i3_status( i3_status ),
.i4_status( i4_status ),
.i6_status( i6_status ),
.i3_full( i3_full ),
.i4_full( i4_full ),
.i6_full( i6_full ),
.oc0_cfg( oc0_cfg ),
.oc1_cfg( oc1_cfg ),
.oc2_cfg( oc2_cfg ),
.oc3_cfg( oc3_cfg ),
.oc4_cfg( oc4_cfg ),
.oc5_cfg( oc5_cfg ),
.ic0_cfg( ic0_cfg ),
.ic1_cfg( ic1_cfg ),
.ic2_cfg( ic2_cfg ),
.dma_req( dma_req_o ),
.dma_ack( dma_ack_i )
);
ac97_int u17(
.clk( clk ),
.rst( rst_i ),
.int_set( oc0_int_set ),
.cfg( oc0_cfg ),
.status( o3_status ),
.full_empty( o3_empty ),
.full( o3_full ),
.empty( o3_empty ),
.re( o3_re ),
.we( o3_we )
);
ac97_int u18(
.clk( clk ),
.rst( rst_i ),
.int_set( oc1_int_set ),
.cfg( oc1_cfg ),
.status( o4_status ),
.full_empty( o4_empty ),
.full( o4_full ),
.empty( o4_empty ),
.re( o4_re ),
.we( o4_we )
);
`ifdef AC97_CENTER
ac97_int u19(
.clk( clk ),
.rst( rst_i ),
.int_set( oc2_int_set ),
.cfg( oc2_cfg ),
.status( o6_status ),
.full_empty( o6_empty ),
.full( o6_full ),
.empty( o6_empty ),
.re( o6_re ),
.we( o6_we )
);
`else
assign oc2_int_set = 1'b0;
`endif
`ifdef AC97_SURROUND
ac97_int u20(
.clk( clk ),
.rst( rst_i ),
.int_set( oc3_int_set ),
.cfg( oc3_cfg ),
.status( o7_status ),
.full_empty( o7_empty ),
.full( o7_full ),
.empty( o7_empty ),
.re( o7_re ),
.we( o7_we )
);
ac97_int u21(
.clk( clk ),
.rst( rst_i ),
.int_set( oc4_int_set ),
.cfg( oc4_cfg ),
.status( o8_status ),
.full_empty( o8_empty ),
.full( o8_full ),
.empty( o8_empty ),
.re( o8_re ),
.we( o8_we )
);
`else
assign oc3_int_set = 1'b0;
assign oc4_int_set = 1'b0;
`endif
`ifdef AC97_LFE
ac97_int u22(
.clk( clk ),
.rst( rst_i ),
.int_set( oc5_int_set ),
.cfg( oc5_cfg ),
.status( o9_status ),
.full_empty( o9_empty ),
.full( o9_full ),
.empty( o9_empty ),
.re( o9_re ),
.we( o9_we )
);
`else
assign oc5_int_set = 1'b0;
`endif
`ifdef AC97_SIN
ac97_int u23(
.clk( clk ),
.rst( rst_i ),
.int_set( ic0_int_set ),
.cfg( ic0_cfg ),
.status( i3_status ),
.full_empty( i3_full ),
.full( i3_full ),
.empty( i3_empty ),
.re( i3_re ),
.we( i3_we )
);
ac97_int u24(
.clk( clk ),
.rst( rst_i ),
.int_set( ic1_int_set ),
.cfg( ic1_cfg ),
.status( i4_status ),
.full_empty( i4_full ),
.full( i4_full ),
.empty( i4_empty ),
.re( i4_re ),
.we( i4_we )
);
`else
assign ic0_int_set = 1'b0;
assign ic1_int_set = 1'b0;
`endif
`ifdef AC97_MICIN
ac97_int u25(
.clk( clk ),
.rst( rst_i ),
.int_set( ic2_int_set ),
.cfg( ic2_cfg ),
.status( i6_status ),
.full_empty( i6_full ),
.full( i6_full ),
.empty( i6_empty ),
.re( i6_re ),
.we( i6_we )
);
`else
assign ic2_int_set = 1'b0;
`endif
ac97_rst u26(
.clk( clk ),
.rst( rst_i ),
.rst_force( ac97_rst_force ),
.ps_ce( ps_ce ),
.ac97_rst_( ac97_reset_pad_o_ )
);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// WISHBONE Interface Module ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_wb_if.v,v 1.4 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_wb_if.v,v $
// Revision 1.4 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.3 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:16 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_wb_if(clk, rst,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
adr, dout, rf_din, i3_din, i4_din, i6_din,
rf_we, rf_re, o3_we, o4_we, o6_we, o7_we, o8_we, o9_we,
i3_re, i4_re, i6_re
);
input clk,rst;
// WISHBONE Interface
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
// Internal Interface
output [3:0] adr;
output [31:0] dout;
input [31:0] rf_din, i3_din, i4_din, i6_din;
output rf_we;
output rf_re;
output o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
output i3_re, i4_re, i6_re;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] wb_data_o;
reg [31:0] dout;
reg wb_ack_o;
reg rf_we;
reg o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
reg i3_re, i4_re, i6_re;
reg we1, we2;
wire we;
reg re2, re1;
wire re;
////////////////////////////////////////////////////////////////////
//
// Modules
//
assign adr = wb_addr_i[5:2];
assign wb_err_o = 1'b0;
always @(posedge clk)
dout <= #1 wb_data_i;
always @(posedge clk)
case(wb_addr_i[6:2]) // synopsys parallel_case full_case
5'he: wb_data_o <= #1 i3_din;
5'hf: wb_data_o <= #1 i4_din;
5'h10: wb_data_o <= #1 i6_din;
default: wb_data_o <= #1 rf_din;
endcase
always @(posedge clk)
re1 <= #1 !re2 & wb_cyc_i & wb_stb_i & !wb_we_i & `AC97_REG_SEL;
always @(posedge clk)
re2 <= #1 re & wb_cyc_i & wb_stb_i & !wb_we_i ;
assign re = re1 & !re2 & wb_cyc_i & wb_stb_i & !wb_we_i;
assign rf_re = re & (wb_addr_i[6:2] < 5'h8);
always @(posedge clk)
we1 <= #1 !we & wb_cyc_i & wb_stb_i & wb_we_i & `AC97_REG_SEL;
always @(posedge clk)
we2 <= #1 we1 & wb_cyc_i & wb_stb_i & wb_we_i;
assign we = we1 & !we2 & wb_cyc_i & wb_stb_i & wb_we_i;
always @(posedge clk)
wb_ack_o <= #1 (re | we) & wb_cyc_i & wb_stb_i & ~wb_ack_o;
always @(posedge clk)
rf_we <= #1 we & (wb_addr_i[6:2] < 5'h8);
always @(posedge clk)
o3_we <= #1 we & (wb_addr_i[6:2] == 5'h8);
always @(posedge clk)
o4_we <= #1 we & (wb_addr_i[6:2] == 5'h9);
always @(posedge clk)
o6_we <= #1 we & (wb_addr_i[6:2] == 5'ha);
always @(posedge clk)
o7_we <= #1 we & (wb_addr_i[6:2] == 5'hb);
always @(posedge clk)
o8_we <= #1 we & (wb_addr_i[6:2] == 5'hc);
always @(posedge clk)
o9_we <= #1 we & (wb_addr_i[6:2] == 5'hd);
always @(posedge clk)
i3_re <= #1 re & (wb_addr_i[6:2] == 5'he);
always @(posedge clk)
i4_re <= #1 re & (wb_addr_i[6:2] == 5'hf);
always @(posedge clk)
i6_re <= #1 re & (wb_addr_i[6:2] == 5'h10);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// AES Cipher Top Level ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: aes_cipher_top.v,v 1.1.1.1 2002/11/09 11:22:48 rudi Exp $
//
// $Date: 2002/11/09 11:22:48 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: aes_cipher_top.v,v $
// Revision 1.1.1.1 2002/11/09 11:22:48 rudi
// Initial Checkin
//
//
//
//
//
//
`include "timescale.v"
module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out );
input clk, rst;
input ld;
output done;
input [127:0] key;
input [127:0] text_in;
output [127:0] text_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [31:0] w0, w1, w2, w3;
reg [127:0] text_in_r;
reg [127:0] text_out;
reg [7:0] sa00, sa01, sa02, sa03;
reg [7:0] sa10, sa11, sa12, sa13;
reg [7:0] sa20, sa21, sa22, sa23;
reg [7:0] sa30, sa31, sa32, sa33;
wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
wire [7:0] sa00_mc, sa01_mc, sa02_mc, sa03_mc;
wire [7:0] sa10_mc, sa11_mc, sa12_mc, sa13_mc;
wire [7:0] sa20_mc, sa21_mc, sa22_mc, sa23_mc;
wire [7:0] sa30_mc, sa31_mc, sa32_mc, sa33_mc;
reg done, ld_r;
reg [3:0] dcnt;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
if(!rst) dcnt <= #1 4'h0;
else
if(ld) dcnt <= #1 4'hb;
else
if(|dcnt) dcnt <= #1 dcnt - 4'h1;
always @(posedge clk) done <= #1 !(|dcnt[3:1]) & dcnt[0] & !ld;
always @(posedge clk) if(ld) text_in_r <= #1 text_in;
always @(posedge clk) ld_r <= #1 ld;
////////////////////////////////////////////////////////////////////
//
// Initial Permutation (AddRoundKey)
//
always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
////////////////////////////////////////////////////////////////////
//
// Round Permutations
//
assign sa00_sr = sa00_sub;
assign sa01_sr = sa01_sub;
assign sa02_sr = sa02_sub;
assign sa03_sr = sa03_sub;
assign sa10_sr = sa11_sub;
assign sa11_sr = sa12_sub;
assign sa12_sr = sa13_sub;
assign sa13_sr = sa10_sub;
assign sa20_sr = sa22_sub;
assign sa21_sr = sa23_sub;
assign sa22_sr = sa20_sub;
assign sa23_sr = sa21_sub;
assign sa30_sr = sa33_sub;
assign sa31_sr = sa30_sub;
assign sa32_sr = sa31_sub;
assign sa33_sr = sa32_sub;
assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc} = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc} = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc} = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc} = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);
assign sa00_next = sa00_mc ^ w0[31:24];
assign sa01_next = sa01_mc ^ w1[31:24];
assign sa02_next = sa02_mc ^ w2[31:24];
assign sa03_next = sa03_mc ^ w3[31:24];
assign sa10_next = sa10_mc ^ w0[23:16];
assign sa11_next = sa11_mc ^ w1[23:16];
assign sa12_next = sa12_mc ^ w2[23:16];
assign sa13_next = sa13_mc ^ w3[23:16];
assign sa20_next = sa20_mc ^ w0[15:08];
assign sa21_next = sa21_mc ^ w1[15:08];
assign sa22_next = sa22_mc ^ w2[15:08];
assign sa23_next = sa23_mc ^ w3[15:08];
assign sa30_next = sa30_mc ^ w0[07:00];
assign sa31_next = sa31_mc ^ w1[07:00];
assign sa32_next = sa32_mc ^ w2[07:00];
assign sa33_next = sa33_mc ^ w3[07:00];
////////////////////////////////////////////////////////////////////
//
// Final text output
//
always @(posedge clk) text_out[127:120] <= #1 sa00_sr ^ w0[31:24];
always @(posedge clk) text_out[095:088] <= #1 sa01_sr ^ w1[31:24];
always @(posedge clk) text_out[063:056] <= #1 sa02_sr ^ w2[31:24];
always @(posedge clk) text_out[031:024] <= #1 sa03_sr ^ w3[31:24];
always @(posedge clk) text_out[119:112] <= #1 sa10_sr ^ w0[23:16];
always @(posedge clk) text_out[087:080] <= #1 sa11_sr ^ w1[23:16];
always @(posedge clk) text_out[055:048] <= #1 sa12_sr ^ w2[23:16];
always @(posedge clk) text_out[023:016] <= #1 sa13_sr ^ w3[23:16];
always @(posedge clk) text_out[111:104] <= #1 sa20_sr ^ w0[15:08];
always @(posedge clk) text_out[079:072] <= #1 sa21_sr ^ w1[15:08];
always @(posedge clk) text_out[047:040] <= #1 sa22_sr ^ w2[15:08];
always @(posedge clk) text_out[015:008] <= #1 sa23_sr ^ w3[15:08];
always @(posedge clk) text_out[103:096] <= #1 sa30_sr ^ w0[07:00];
always @(posedge clk) text_out[071:064] <= #1 sa31_sr ^ w1[07:00];
always @(posedge clk) text_out[039:032] <= #1 sa32_sr ^ w2[07:00];
always @(posedge clk) text_out[007:000] <= #1 sa33_sr ^ w3[07:00];
////////////////////////////////////////////////////////////////////
//
// Generic Functions
//
function [31:0] mix_col;
input [7:0] s0,s1,s2,s3;
reg [7:0] s0_o,s1_o,s2_o,s3_o;
begin
mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
end
endfunction
function [7:0] xtime;
input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
endfunction
////////////////////////////////////////////////////////////////////
//
// Modules
//
aes_key_expand_128 u0(
.clk( clk ),
.kld( ld ),
.key( key ),
.wo_0( w0 ),
.wo_1( w1 ),
.wo_2( w2 ),
.wo_3( w3 ));
aes_sbox us00( .a( sa00 ), .d( sa00_sub ));
aes_sbox us01( .a( sa01 ), .d( sa01_sub ));
aes_sbox us02( .a( sa02 ), .d( sa02_sub ));
aes_sbox us03( .a( sa03 ), .d( sa03_sub ));
aes_sbox us10( .a( sa10 ), .d( sa10_sub ));
aes_sbox us11( .a( sa11 ), .d( sa11_sub ));
aes_sbox us12( .a( sa12 ), .d( sa12_sub ));
aes_sbox us13( .a( sa13 ), .d( sa13_sub ));
aes_sbox us20( .a( sa20 ), .d( sa20_sub ));
aes_sbox us21( .a( sa21 ), .d( sa21_sub ));
aes_sbox us22( .a( sa22 ), .d( sa22_sub ));
aes_sbox us23( .a( sa23 ), .d( sa23_sub ));
aes_sbox us30( .a( sa30 ), .d( sa30_sub ));
aes_sbox us31( .a( sa31 ), .d( sa31_sub ));
aes_sbox us32( .a( sa32 ), .d( sa32_sub ));
aes_sbox us33( .a( sa33 ), .d( sa33_sub ));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// AES Inverse Cipher Top Level ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: aes_inv_cipher_top.v,v 1.1.1.1 2002/11/09 11:22:53 rudi Exp $
//
// $Date: 2002/11/09 11:22:53 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: aes_inv_cipher_top.v,v $
// Revision 1.1.1.1 2002/11/09 11:22:53 rudi
// Initial Checkin
//
//
//
//
//
//
`include "timescale.v"
module aes_inv_cipher_top(clk, rst, kld, ld, done, key, text_in, text_out );
input clk, rst;
input kld, ld;
output done;
input [127:0] key;
input [127:0] text_in;
output [127:0] text_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [31:0] wk0, wk1, wk2, wk3;
reg [31:0] w0, w1, w2, w3;
reg [127:0] text_in_r;
reg [127:0] text_out;
reg [7:0] sa00, sa01, sa02, sa03;
reg [7:0] sa10, sa11, sa12, sa13;
reg [7:0] sa20, sa21, sa22, sa23;
reg [7:0] sa30, sa31, sa32, sa33;
wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
wire [7:0] sa00_ark, sa01_ark, sa02_ark, sa03_ark;
wire [7:0] sa10_ark, sa11_ark, sa12_ark, sa13_ark;
wire [7:0] sa20_ark, sa21_ark, sa22_ark, sa23_ark;
wire [7:0] sa30_ark, sa31_ark, sa32_ark, sa33_ark;
reg ld_r, go, done;
reg [3:0] dcnt;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
if(!rst) dcnt <= #1 4'h0;
else
if(done) dcnt <= #1 4'h0;
else
if(ld) dcnt <= #1 4'h1;
else
if(go) dcnt <= #1 dcnt + 4'h1;
always @(posedge clk) done <= #1 (dcnt==4'hb) & !ld;
always @(posedge clk)
if(!rst) go <= #1 1'b0;
else
if(ld) go <= #1 1'b1;
else
if(done) go <= #1 1'b0;
always @(posedge clk) if(ld) text_in_r <= #1 text_in;
always @(posedge clk) ld_r <= #1 ld;
////////////////////////////////////////////////////////////////////
//
// Initial Permutation
//
always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
////////////////////////////////////////////////////////////////////
//
// Round Permutations
//
assign sa00_sr = sa00;
assign sa01_sr = sa01;
assign sa02_sr = sa02;
assign sa03_sr = sa03;
assign sa10_sr = sa13;
assign sa11_sr = sa10;
assign sa12_sr = sa11;
assign sa13_sr = sa12;
assign sa20_sr = sa22;
assign sa21_sr = sa23;
assign sa22_sr = sa20;
assign sa23_sr = sa21;
assign sa30_sr = sa31;
assign sa31_sr = sa32;
assign sa32_sr = sa33;
assign sa33_sr = sa30;
assign sa00_ark = sa00_sub ^ w0[31:24];
assign sa01_ark = sa01_sub ^ w1[31:24];
assign sa02_ark = sa02_sub ^ w2[31:24];
assign sa03_ark = sa03_sub ^ w3[31:24];
assign sa10_ark = sa10_sub ^ w0[23:16];
assign sa11_ark = sa11_sub ^ w1[23:16];
assign sa12_ark = sa12_sub ^ w2[23:16];
assign sa13_ark = sa13_sub ^ w3[23:16];
assign sa20_ark = sa20_sub ^ w0[15:08];
assign sa21_ark = sa21_sub ^ w1[15:08];
assign sa22_ark = sa22_sub ^ w2[15:08];
assign sa23_ark = sa23_sub ^ w3[15:08];
assign sa30_ark = sa30_sub ^ w0[07:00];
assign sa31_ark = sa31_sub ^ w1[07:00];
assign sa32_ark = sa32_sub ^ w2[07:00];
assign sa33_ark = sa33_sub ^ w3[07:00];
assign {sa00_next, sa10_next, sa20_next, sa30_next} = inv_mix_col(sa00_ark,sa10_ark,sa20_ark,sa30_ark);
assign {sa01_next, sa11_next, sa21_next, sa31_next} = inv_mix_col(sa01_ark,sa11_ark,sa21_ark,sa31_ark);
assign {sa02_next, sa12_next, sa22_next, sa32_next} = inv_mix_col(sa02_ark,sa12_ark,sa22_ark,sa32_ark);
assign {sa03_next, sa13_next, sa23_next, sa33_next} = inv_mix_col(sa03_ark,sa13_ark,sa23_ark,sa33_ark);
////////////////////////////////////////////////////////////////////
//
// Final Text Output
//
always @(posedge clk) text_out[127:120] <= #1 sa00_ark;
always @(posedge clk) text_out[095:088] <= #1 sa01_ark;
always @(posedge clk) text_out[063:056] <= #1 sa02_ark;
always @(posedge clk) text_out[031:024] <= #1 sa03_ark;
always @(posedge clk) text_out[119:112] <= #1 sa10_ark;
always @(posedge clk) text_out[087:080] <= #1 sa11_ark;
always @(posedge clk) text_out[055:048] <= #1 sa12_ark;
always @(posedge clk) text_out[023:016] <= #1 sa13_ark;
always @(posedge clk) text_out[111:104] <= #1 sa20_ark;
always @(posedge clk) text_out[079:072] <= #1 sa21_ark;
always @(posedge clk) text_out[047:040] <= #1 sa22_ark;
always @(posedge clk) text_out[015:008] <= #1 sa23_ark;
always @(posedge clk) text_out[103:096] <= #1 sa30_ark;
always @(posedge clk) text_out[071:064] <= #1 sa31_ark;
always @(posedge clk) text_out[039:032] <= #1 sa32_ark;
always @(posedge clk) text_out[007:000] <= #1 sa33_ark;
////////////////////////////////////////////////////////////////////
//
// Generic Functions
//
function [31:0] inv_mix_col;
input [7:0] s0,s1,s2,s3;
begin
inv_mix_col[31:24]=pmul_e(s0)^pmul_b(s1)^pmul_d(s2)^pmul_9(s3);
inv_mix_col[23:16]=pmul_9(s0)^pmul_e(s1)^pmul_b(s2)^pmul_d(s3);
inv_mix_col[15:08]=pmul_d(s0)^pmul_9(s1)^pmul_e(s2)^pmul_b(s3);
inv_mix_col[07:00]=pmul_b(s0)^pmul_d(s1)^pmul_9(s2)^pmul_e(s3);
end
endfunction
// Some synthesis tools don't like xtime being called recursevly ...
function [7:0] pmul_e;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_e=eight^four^two;
end
endfunction
function [7:0] pmul_9;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_9=eight^b;
end
endfunction
function [7:0] pmul_d;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_d=eight^four^b;
end
endfunction
function [7:0] pmul_b;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_b=eight^two^b;
end
endfunction
function [7:0] xtime;
input [7:0] b;xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
endfunction
////////////////////////////////////////////////////////////////////
//
// Key Buffer
//
reg [127:0] kb[10:0];
reg [3:0] kcnt;
reg kdone;
reg kb_ld;
always @(posedge clk)
if(!rst) kcnt <= #1 4'ha;
else
if(kld) kcnt <= #1 4'ha;
else
if(kb_ld) kcnt <= #1 kcnt - 4'h1;
always @(posedge clk)
if(!rst) kb_ld <= #1 1'b0;
else
if(kld) kb_ld <= #1 1'b1;
else
if(kcnt==4'h0) kb_ld <= #1 1'b0;
always @(posedge clk) kdone <= #1 (kcnt==4'h0) & !kld;
always @(posedge clk) if(kb_ld) kb[kcnt] <= #1 {wk3, wk2, wk1, wk0};
always @(posedge clk) {w3, w2, w1, w0} <= #1 kb[dcnt];
////////////////////////////////////////////////////////////////////
//
// Modules
//
aes_key_expand_128 u0(
.clk( clk ),
.kld( kld ),
.key( key ),
.wo_0( wk0 ),
.wo_1( wk1 ),
.wo_2( wk2 ),
.wo_3( wk3 ));
aes_inv_sbox us00( .a( sa00_sr ), .d( sa00_sub ));
aes_inv_sbox us01( .a( sa01_sr ), .d( sa01_sub ));
aes_inv_sbox us02( .a( sa02_sr ), .d( sa02_sub ));
aes_inv_sbox us03( .a( sa03_sr ), .d( sa03_sub ));
aes_inv_sbox us10( .a( sa10_sr ), .d( sa10_sub ));
aes_inv_sbox us11( .a( sa11_sr ), .d( sa11_sub ));
aes_inv_sbox us12( .a( sa12_sr ), .d( sa12_sub ));
aes_inv_sbox us13( .a( sa13_sr ), .d( sa13_sub ));
aes_inv_sbox us20( .a( sa20_sr ), .d( sa20_sub ));
aes_inv_sbox us21( .a( sa21_sr ), .d( sa21_sub ));
aes_inv_sbox us22( .a( sa22_sr ), .d( sa22_sub ));
aes_inv_sbox us23( .a( sa23_sr ), .d( sa23_sub ));
aes_inv_sbox us30( .a( sa30_sr ), .d( sa30_sub ));
aes_inv_sbox us31( .a( sa31_sr ), .d( sa31_sub ));
aes_inv_sbox us32( .a( sa32_sr ), .d( sa32_sub ));
aes_inv_sbox us33( .a( sa33_sr ), .d( sa33_sub ));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// AES Inverse SBOX (ROM) ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: aes_inv_sbox.v,v 1.1.1.1 2002/11/09 11:22:55 rudi Exp $
//
// $Date: 2002/11/09 11:22:55 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: aes_inv_sbox.v,v $
// Revision 1.1.1.1 2002/11/09 11:22:55 rudi
// Initial Checkin
//
//
//
//
//
//
`include "timescale.v"
module aes_inv_sbox(a,d);
input [7:0] a;
output [7:0] d;
reg [7:0] d;
always @(a)
case(a) // synopsys full_case parallel_case
8'h00: d=8'h52;
8'h01: d=8'h09;
8'h02: d=8'h6a;
8'h03: d=8'hd5;
8'h04: d=8'h30;
8'h05: d=8'h36;
8'h06: d=8'ha5;
8'h07: d=8'h38;
8'h08: d=8'hbf;
8'h09: d=8'h40;
8'h0a: d=8'ha3;
8'h0b: d=8'h9e;
8'h0c: d=8'h81;
8'h0d: d=8'hf3;
8'h0e: d=8'hd7;
8'h0f: d=8'hfb;
8'h10: d=8'h7c;
8'h11: d=8'he3;
8'h12: d=8'h39;
8'h13: d=8'h82;
8'h14: d=8'h9b;
8'h15: d=8'h2f;
8'h16: d=8'hff;
8'h17: d=8'h87;
8'h18: d=8'h34;
8'h19: d=8'h8e;
8'h1a: d=8'h43;
8'h1b: d=8'h44;
8'h1c: d=8'hc4;
8'h1d: d=8'hde;
8'h1e: d=8'he9;
8'h1f: d=8'hcb;
8'h20: d=8'h54;
8'h21: d=8'h7b;
8'h22: d=8'h94;
8'h23: d=8'h32;
8'h24: d=8'ha6;
8'h25: d=8'hc2;
8'h26: d=8'h23;
8'h27: d=8'h3d;
8'h28: d=8'hee;
8'h29: d=8'h4c;
8'h2a: d=8'h95;
8'h2b: d=8'h0b;
8'h2c: d=8'h42;
8'h2d: d=8'hfa;
8'h2e: d=8'hc3;
8'h2f: d=8'h4e;
8'h30: d=8'h08;
8'h31: d=8'h2e;
8'h32: d=8'ha1;
8'h33: d=8'h66;
8'h34: d=8'h28;
8'h35: d=8'hd9;
8'h36: d=8'h24;
8'h37: d=8'hb2;
8'h38: d=8'h76;
8'h39: d=8'h5b;
8'h3a: d=8'ha2;
8'h3b: d=8'h49;
8'h3c: d=8'h6d;
8'h3d: d=8'h8b;
8'h3e: d=8'hd1;
8'h3f: d=8'h25;
8'h40: d=8'h72;
8'h41: d=8'hf8;
8'h42: d=8'hf6;
8'h43: d=8'h64;
8'h44: d=8'h86;
8'h45: d=8'h68;
8'h46: d=8'h98;
8'h47: d=8'h16;
8'h48: d=8'hd4;
8'h49: d=8'ha4;
8'h4a: d=8'h5c;
8'h4b: d=8'hcc;
8'h4c: d=8'h5d;
8'h4d: d=8'h65;
8'h4e: d=8'hb6;
8'h4f: d=8'h92;
8'h50: d=8'h6c;
8'h51: d=8'h70;
8'h52: d=8'h48;
8'h53: d=8'h50;
8'h54: d=8'hfd;
8'h55: d=8'hed;
8'h56: d=8'hb9;
8'h57: d=8'hda;
8'h58: d=8'h5e;
8'h59: d=8'h15;
8'h5a: d=8'h46;
8'h5b: d=8'h57;
8'h5c: d=8'ha7;
8'h5d: d=8'h8d;
8'h5e: d=8'h9d;
8'h5f: d=8'h84;
8'h60: d=8'h90;
8'h61: d=8'hd8;
8'h62: d=8'hab;
8'h63: d=8'h00;
8'h64: d=8'h8c;
8'h65: d=8'hbc;
8'h66: d=8'hd3;
8'h67: d=8'h0a;
8'h68: d=8'hf7;
8'h69: d=8'he4;
8'h6a: d=8'h58;
8'h6b: d=8'h05;
8'h6c: d=8'hb8;
8'h6d: d=8'hb3;
8'h6e: d=8'h45;
8'h6f: d=8'h06;
8'h70: d=8'hd0;
8'h71: d=8'h2c;
8'h72: d=8'h1e;
8'h73: d=8'h8f;
8'h74: d=8'hca;
8'h75: d=8'h3f;
8'h76: d=8'h0f;
8'h77: d=8'h02;
8'h78: d=8'hc1;
8'h79: d=8'haf;
8'h7a: d=8'hbd;
8'h7b: d=8'h03;
8'h7c: d=8'h01;
8'h7d: d=8'h13;
8'h7e: d=8'h8a;
8'h7f: d=8'h6b;
8'h80: d=8'h3a;
8'h81: d=8'h91;
8'h82: d=8'h11;
8'h83: d=8'h41;
8'h84: d=8'h4f;
8'h85: d=8'h67;
8'h86: d=8'hdc;
8'h87: d=8'hea;
8'h88: d=8'h97;
8'h89: d=8'hf2;
8'h8a: d=8'hcf;
8'h8b: d=8'hce;
8'h8c: d=8'hf0;
8'h8d: d=8'hb4;
8'h8e: d=8'he6;
8'h8f: d=8'h73;
8'h90: d=8'h96;
8'h91: d=8'hac;
8'h92: d=8'h74;
8'h93: d=8'h22;
8'h94: d=8'he7;
8'h95: d=8'had;
8'h96: d=8'h35;
8'h97: d=8'h85;
8'h98: d=8'he2;
8'h99: d=8'hf9;
8'h9a: d=8'h37;
8'h9b: d=8'he8;
8'h9c: d=8'h1c;
8'h9d: d=8'h75;
8'h9e: d=8'hdf;
8'h9f: d=8'h6e;
8'ha0: d=8'h47;
8'ha1: d=8'hf1;
8'ha2: d=8'h1a;
8'ha3: d=8'h71;
8'ha4: d=8'h1d;
8'ha5: d=8'h29;
8'ha6: d=8'hc5;
8'ha7: d=8'h89;
8'ha8: d=8'h6f;
8'ha9: d=8'hb7;
8'haa: d=8'h62;
8'hab: d=8'h0e;
8'hac: d=8'haa;
8'had: d=8'h18;
8'hae: d=8'hbe;
8'haf: d=8'h1b;
8'hb0: d=8'hfc;
8'hb1: d=8'h56;
8'hb2: d=8'h3e;
8'hb3: d=8'h4b;
8'hb4: d=8'hc6;
8'hb5: d=8'hd2;
8'hb6: d=8'h79;
8'hb7: d=8'h20;
8'hb8: d=8'h9a;
8'hb9: d=8'hdb;
8'hba: d=8'hc0;
8'hbb: d=8'hfe;
8'hbc: d=8'h78;
8'hbd: d=8'hcd;
8'hbe: d=8'h5a;
8'hbf: d=8'hf4;
8'hc0: d=8'h1f;
8'hc1: d=8'hdd;
8'hc2: d=8'ha8;
8'hc3: d=8'h33;
8'hc4: d=8'h88;
8'hc5: d=8'h07;
8'hc6: d=8'hc7;
8'hc7: d=8'h31;
8'hc8: d=8'hb1;
8'hc9: d=8'h12;
8'hca: d=8'h10;
8'hcb: d=8'h59;
8'hcc: d=8'h27;
8'hcd: d=8'h80;
8'hce: d=8'hec;
8'hcf: d=8'h5f;
8'hd0: d=8'h60;
8'hd1: d=8'h51;
8'hd2: d=8'h7f;
8'hd3: d=8'ha9;
8'hd4: d=8'h19;
8'hd5: d=8'hb5;
8'hd6: d=8'h4a;
8'hd7: d=8'h0d;
8'hd8: d=8'h2d;
8'hd9: d=8'he5;
8'hda: d=8'h7a;
8'hdb: d=8'h9f;
8'hdc: d=8'h93;
8'hdd: d=8'hc9;
8'hde: d=8'h9c;
8'hdf: d=8'hef;
8'he0: d=8'ha0;
8'he1: d=8'he0;
8'he2: d=8'h3b;
8'he3: d=8'h4d;
8'he4: d=8'hae;
8'he5: d=8'h2a;
8'he6: d=8'hf5;
8'he7: d=8'hb0;
8'he8: d=8'hc8;
8'he9: d=8'heb;
8'hea: d=8'hbb;
8'heb: d=8'h3c;
8'hec: d=8'h83;
8'hed: d=8'h53;
8'hee: d=8'h99;
8'hef: d=8'h61;
8'hf0: d=8'h17;
8'hf1: d=8'h2b;
8'hf2: d=8'h04;
8'hf3: d=8'h7e;
8'hf4: d=8'hba;
8'hf5: d=8'h77;
8'hf6: d=8'hd6;
8'hf7: d=8'h26;
8'hf8: d=8'he1;
8'hf9: d=8'h69;
8'hfa: d=8'h14;
8'hfb: d=8'h63;
8'hfc: d=8'h55;
8'hfd: d=8'h21;
8'hfe: d=8'h0c;
8'hff: d=8'h7d;
endcase
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// AES Key Expand Block (for 128 bit keys) ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: aes_key_expand_128.v,v 1.1.1.1 2002/11/09 11:22:38 rudi Exp $
//
// $Date: 2002/11/09 11:22:38 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: aes_key_expand_128.v,v $
// Revision 1.1.1.1 2002/11/09 11:22:38 rudi
// Initial Checkin
//
//
//
//
//
//
`include "timescale.v"
module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
input clk;
input kld;
input [127:0] key;
output [31:0] wo_0, wo_1, wo_2, wo_3;
reg [31:0] w[3:0];
wire [31:0] tmp_w;
wire [31:0] subword;
wire [31:0] rcon;
assign wo_0 = w[0];
assign wo_1 = w[1];
assign wo_2 = w[2];
assign wo_3 = w[3];
always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
assign tmp_w = w[3];
aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
aes_rcon r0( .clk(clk), .kld(kld), .out(rcon));
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// AES RCON Block ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: aes_rcon.v,v 1.1.1.1 2002/11/09 11:22:38 rudi Exp $
//
// $Date: 2002/11/09 11:22:38 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: aes_rcon.v,v $
// Revision 1.1.1.1 2002/11/09 11:22:38 rudi
// Initial Checkin
//
//
//
//
//
//
`include "timescale.v"
module aes_rcon(clk, kld, out);
input clk;
input kld;
output [31:0] out;
reg [31:0] out;
reg [3:0] rcnt;
wire [3:0] rcnt_next;
always @(posedge clk)
if(kld) out <= #1 32'h01_00_00_00;
else out <= #1 frcon(rcnt_next);
assign rcnt_next = rcnt + 4'h1;
always @(posedge clk)
if(kld) rcnt <= #1 4'h0;
else rcnt <= #1 rcnt_next;
function [31:0] frcon;
input [3:0] i;
case(i) // synopsys parallel_case
4'h0: frcon=32'h01_00_00_00;
4'h1: frcon=32'h02_00_00_00;
4'h2: frcon=32'h04_00_00_00;
4'h3: frcon=32'h08_00_00_00;
4'h4: frcon=32'h10_00_00_00;
4'h5: frcon=32'h20_00_00_00;
4'h6: frcon=32'h40_00_00_00;
4'h7: frcon=32'h80_00_00_00;
4'h8: frcon=32'h1b_00_00_00;
4'h9: frcon=32'h36_00_00_00;
default: frcon=32'h00_00_00_00;
endcase
endfunction
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// AES SBOX (ROM) ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/aes_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: aes_sbox.v,v 1.1.1.1 2002/11/09 11:22:38 rudi Exp $
//
// $Date: 2002/11/09 11:22:38 $
// $Revision: 1.1.1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: aes_sbox.v,v $
// Revision 1.1.1.1 2002/11/09 11:22:38 rudi
// Initial Checkin
//
//
//
//
//
//
`include "timescale.v"
module aes_sbox(a,d);
input [7:0] a;
output [7:0] d;
reg [7:0] d;
always @(a)
case(a) // synopsys full_case parallel_case
8'h00: d=8'h63;
8'h01: d=8'h7c;
8'h02: d=8'h77;
8'h03: d=8'h7b;
8'h04: d=8'hf2;
8'h05: d=8'h6b;
8'h06: d=8'h6f;
8'h07: d=8'hc5;
8'h08: d=8'h30;
8'h09: d=8'h01;
8'h0a: d=8'h67;
8'h0b: d=8'h2b;
8'h0c: d=8'hfe;
8'h0d: d=8'hd7;
8'h0e: d=8'hab;
8'h0f: d=8'h76;
8'h10: d=8'hca;
8'h11: d=8'h82;
8'h12: d=8'hc9;
8'h13: d=8'h7d;
8'h14: d=8'hfa;
8'h15: d=8'h59;
8'h16: d=8'h47;
8'h17: d=8'hf0;
8'h18: d=8'had;
8'h19: d=8'hd4;
8'h1a: d=8'ha2;
8'h1b: d=8'haf;
8'h1c: d=8'h9c;
8'h1d: d=8'ha4;
8'h1e: d=8'h72;
8'h1f: d=8'hc0;
8'h20: d=8'hb7;
8'h21: d=8'hfd;
8'h22: d=8'h93;
8'h23: d=8'h26;
8'h24: d=8'h36;
8'h25: d=8'h3f;
8'h26: d=8'hf7;
8'h27: d=8'hcc;
8'h28: d=8'h34;
8'h29: d=8'ha5;
8'h2a: d=8'he5;
8'h2b: d=8'hf1;
8'h2c: d=8'h71;
8'h2d: d=8'hd8;
8'h2e: d=8'h31;
8'h2f: d=8'h15;
8'h30: d=8'h04;
8'h31: d=8'hc7;
8'h32: d=8'h23;
8'h33: d=8'hc3;
8'h34: d=8'h18;
8'h35: d=8'h96;
8'h36: d=8'h05;
8'h37: d=8'h9a;
8'h38: d=8'h07;
8'h39: d=8'h12;
8'h3a: d=8'h80;
8'h3b: d=8'he2;
8'h3c: d=8'heb;
8'h3d: d=8'h27;
8'h3e: d=8'hb2;
8'h3f: d=8'h75;
8'h40: d=8'h09;
8'h41: d=8'h83;
8'h42: d=8'h2c;
8'h43: d=8'h1a;
8'h44: d=8'h1b;
8'h45: d=8'h6e;
8'h46: d=8'h5a;
8'h47: d=8'ha0;
8'h48: d=8'h52;
8'h49: d=8'h3b;
8'h4a: d=8'hd6;
8'h4b: d=8'hb3;
8'h4c: d=8'h29;
8'h4d: d=8'he3;
8'h4e: d=8'h2f;
8'h4f: d=8'h84;
8'h50: d=8'h53;
8'h51: d=8'hd1;
8'h52: d=8'h00;
8'h53: d=8'hed;
8'h54: d=8'h20;
8'h55: d=8'hfc;
8'h56: d=8'hb1;
8'h57: d=8'h5b;
8'h58: d=8'h6a;
8'h59: d=8'hcb;
8'h5a: d=8'hbe;
8'h5b: d=8'h39;
8'h5c: d=8'h4a;
8'h5d: d=8'h4c;
8'h5e: d=8'h58;
8'h5f: d=8'hcf;
8'h60: d=8'hd0;
8'h61: d=8'hef;
8'h62: d=8'haa;
8'h63: d=8'hfb;
8'h64: d=8'h43;
8'h65: d=8'h4d;
8'h66: d=8'h33;
8'h67: d=8'h85;
8'h68: d=8'h45;
8'h69: d=8'hf9;
8'h6a: d=8'h02;
8'h6b: d=8'h7f;
8'h6c: d=8'h50;
8'h6d: d=8'h3c;
8'h6e: d=8'h9f;
8'h6f: d=8'ha8;
8'h70: d=8'h51;
8'h71: d=8'ha3;
8'h72: d=8'h40;
8'h73: d=8'h8f;
8'h74: d=8'h92;
8'h75: d=8'h9d;
8'h76: d=8'h38;
8'h77: d=8'hf5;
8'h78: d=8'hbc;
8'h79: d=8'hb6;
8'h7a: d=8'hda;
8'h7b: d=8'h21;
8'h7c: d=8'h10;
8'h7d: d=8'hff;
8'h7e: d=8'hf3;
8'h7f: d=8'hd2;
8'h80: d=8'hcd;
8'h81: d=8'h0c;
8'h82: d=8'h13;
8'h83: d=8'hec;
8'h84: d=8'h5f;
8'h85: d=8'h97;
8'h86: d=8'h44;
8'h87: d=8'h17;
8'h88: d=8'hc4;
8'h89: d=8'ha7;
8'h8a: d=8'h7e;
8'h8b: d=8'h3d;
8'h8c: d=8'h64;
8'h8d: d=8'h5d;
8'h8e: d=8'h19;
8'h8f: d=8'h73;
8'h90: d=8'h60;
8'h91: d=8'h81;
8'h92: d=8'h4f;
8'h93: d=8'hdc;
8'h94: d=8'h22;
8'h95: d=8'h2a;
8'h96: d=8'h90;
8'h97: d=8'h88;
8'h98: d=8'h46;
8'h99: d=8'hee;
8'h9a: d=8'hb8;
8'h9b: d=8'h14;
8'h9c: d=8'hde;
8'h9d: d=8'h5e;
8'h9e: d=8'h0b;
8'h9f: d=8'hdb;
8'ha0: d=8'he0;
8'ha1: d=8'h32;
8'ha2: d=8'h3a;
8'ha3: d=8'h0a;
8'ha4: d=8'h49;
8'ha5: d=8'h06;
8'ha6: d=8'h24;
8'ha7: d=8'h5c;
8'ha8: d=8'hc2;
8'ha9: d=8'hd3;
8'haa: d=8'hac;
8'hab: d=8'h62;
8'hac: d=8'h91;
8'had: d=8'h95;
8'hae: d=8'he4;
8'haf: d=8'h79;
8'hb0: d=8'he7;
8'hb1: d=8'hc8;
8'hb2: d=8'h37;
8'hb3: d=8'h6d;
8'hb4: d=8'h8d;
8'hb5: d=8'hd5;
8'hb6: d=8'h4e;
8'hb7: d=8'ha9;
8'hb8: d=8'h6c;
8'hb9: d=8'h56;
8'hba: d=8'hf4;
8'hbb: d=8'hea;
8'hbc: d=8'h65;
8'hbd: d=8'h7a;
8'hbe: d=8'hae;
8'hbf: d=8'h08;
8'hc0: d=8'hba;
8'hc1: d=8'h78;
8'hc2: d=8'h25;
8'hc3: d=8'h2e;
8'hc4: d=8'h1c;
8'hc5: d=8'ha6;
8'hc6: d=8'hb4;
8'hc7: d=8'hc6;
8'hc8: d=8'he8;
8'hc9: d=8'hdd;
8'hca: d=8'h74;
8'hcb: d=8'h1f;
8'hcc: d=8'h4b;
8'hcd: d=8'hbd;
8'hce: d=8'h8b;
8'hcf: d=8'h8a;
8'hd0: d=8'h70;
8'hd1: d=8'h3e;
8'hd2: d=8'hb5;
8'hd3: d=8'h66;
8'hd4: d=8'h48;
8'hd5: d=8'h03;
8'hd6: d=8'hf6;
8'hd7: d=8'h0e;
8'hd8: d=8'h61;
8'hd9: d=8'h35;
8'hda: d=8'h57;
8'hdb: d=8'hb9;
8'hdc: d=8'h86;
8'hdd: d=8'hc1;
8'hde: d=8'h1d;
8'hdf: d=8'h9e;
8'he0: d=8'he1;
8'he1: d=8'hf8;
8'he2: d=8'h98;
8'he3: d=8'h11;
8'he4: d=8'h69;
8'he5: d=8'hd9;
8'he6: d=8'h8e;
8'he7: d=8'h94;
8'he8: d=8'h9b;
8'he9: d=8'h1e;
8'hea: d=8'h87;
8'heb: d=8'he9;
8'hec: d=8'hce;
8'hed: d=8'h55;
8'hee: d=8'h28;
8'hef: d=8'hdf;
8'hf0: d=8'h8c;
8'hf1: d=8'ha1;
8'hf2: d=8'h89;
8'hf3: d=8'h0d;
8'hf4: d=8'hbf;
8'hf5: d=8'he6;
8'hf6: d=8'h42;
8'hf7: d=8'h68;
8'hf8: d=8'h41;
8'hf9: d=8'h99;
8'hfa: d=8'h2d;
8'hfb: d=8'h0f;
8'hfc: d=8'hb0;
8'hfd: d=8'h54;
8'hfe: d=8'hbb;
8'hff: d=8'h16;
endcase
endmodule
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`timescale 1ns / 10ps
|
/****************************************************************************
AddSub unit
- Should perform ADD, ADDU, SUBU, SUB, SLT, SLTU
is_slt signext addsub
op[2] op[1] op[0] | Operation
0 0 0 0 SUBU
2 0 1 0 SUB
1 0 0 1 ADDU
3 0 1 1 ADD
4 1 0 0 SLTU
6 1 1 0 SLT
****************************************************************************/
module addersub (
opA, opB,
op,
result,
result_slt );
parameter WIDTH=32;
input [WIDTH-1:0] opA;
input [WIDTH-1:0] opB;
//input carry_in;
input [3-1:0] op;
output [WIDTH-1:0] result;
output result_slt;
wire carry_out;
wire [WIDTH:0] sum;
// Mux between sum, and slt
wire is_slt;
wire signext;
wire addsub;
assign is_slt=op[2];
assign signext=op[1];
assign addsub=op[0];
assign result=sum[WIDTH-1:0];
//assign result_slt[WIDTH-1:1]={31{1'b0}};
//assign result_slt[0]=sum[WIDTH];
assign result_slt=sum[WIDTH];
lpm_add_sub adder_inst(
.dataa({signext&opA[WIDTH-1],opA}),
.datab({signext&opB[WIDTH-1],opB}),
.cin(~addsub),
.add_sub(addsub),
.result(sum)
// synopsys translate_off
,
.cout (),
.clken (),
.clock (),
.overflow (),
.aclr ()
// synopsys translate_on
);
defparam
adder_inst.lpm_width=WIDTH+1,
adder_inst.lpm_representation="SIGNED";
assign carry_out=sum[WIDTH];
endmodule
|
module branchresolve ( en, rs, rt, eq, ne, ltz, lez, gtz, gez, eqz);
parameter WIDTH=32; //Deepak : Change from parameter to define
input en;
input [WIDTH-1:0] rs;
input [WIDTH-1:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq=(en)&(rs==rt);
assign ne=(en)&~eq;
assign eqz=(en)&~(|rs);
assign ltz=(en)&rs[WIDTH-1];
assign lez=(en)&rs[WIDTH-1] | eqz;
assign gtz=(en)&(~rs[WIDTH-1]) & ~eqz;
assign gez=(en)&(~rs[WIDTH-1]);
endmodule
|
/****************************************************************************
Generic Register
****************************************************************************/
module register(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Register - synchronous reset
****************************************************************************/
module register_sync(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register
- Special component, components starting with "pipereg" have
their enables treated independently of instructrions that use them.
- They are enabled whenever the stage is active and not stalled
****************************************************************************/
module pipereg(d,clk,resetn,en,squashn,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register 2 -OLD: If not enabled, queues squash
- This piperegister stalls the reset signal as well
module pipereg_full(d,clk,resetn,squashn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg squash_save;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || (squashn==0 && en==1) || (squash_save&en))
q<=0;
else if (en==1)
q<=d;
end
always @(posedge clk)
begin
if (resetn==1 && squashn==0 && en==0)
squash_save<=1;
else
squash_save<=0;
end
endmodule
****************************************************************************/
/****************************************************************************
One cycle Stall circuit
****************************************************************************/
module onecyclestall(request,clk,resetn,stalled);
input request;
input clk;
input resetn;
output stalled;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(request or T)
begin
case(T)
1'b0: Tnext=request;
1'b1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
assign stalled=(request&~T);
endmodule
/****************************************************************************
Multi cycle Stall circuit - with wait signal
- One FF plus one 2:1 mux to stall 1st cycle on request, then wait
- this makes wait don't care for the first cycle
****************************************************************************/
module multicyclestall(request, devwait,clk,resetn,stalled);
input request;
input devwait;
input clk;
input resetn;
output stalled;
reg T;
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=stalled;
assign stalled=(T) ? devwait : request;
endmodule
/****************************************************************************
One cycle - Pipeline delay register
****************************************************************************/
module pipedelayreg(d,en,clk,resetn,squashn,dst,stalled,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input [4:0] dst;
input en;
input clk;
input resetn;
input squashn;
output stalled;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(en or T or dst)
begin
case(T)
0: Tnext=en&(|dst);
1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
assign stalled=(en&~T&(|dst));
endmodule
/****************************************************************************
Fake Delay
****************************************************************************/
module fakedelay(d,clk,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input clk;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Zeroer
****************************************************************************/
module zeroer(d,en,q);
parameter WIDTH=32;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q= (en) ? d : 0;
endmodule
/****************************************************************************
NOP - used to hack position of multiplexors
****************************************************************************/
module nop(d,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Const
****************************************************************************/
//Deepak : Changed const to constant to resolve compilation error
module constant (out);
parameter WIDTH=32;
parameter VAL=31;
output [WIDTH-1:0] out;
assign out=VAL;
endmodule
/****************************************************************************
Branch detector
****************************************************************************/
module branch_detector(opcode, func, is_branch);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
assign is_special=!(|opcode);
assign is_branch=((!(|opcode[5:3])) && !is_special) ||
((is_special)&&(func[5:3]==3'b001));
endmodule
|