\r\n
\r\n\r\n---\r\n**STEP 3.** Trying to use `openroad` to do `Floorplan` (FAILED)\r\n\r\nMake a `results` folder then set its path to the `RESULTS_DIR` variable for `openroad` use to store output files\r\n```\r\n$ mkdir results\r\n$ set RESULTS_DIR results\r\n```\r\n\r\nAfter I ran `read_design -json and_gate.json` failed (missing `read_design` command), I tried `read_verilog and_gate.v` but it's still failed.\r\n\r\n```bash\r\nubuntu@ubuntu-linux:~/Desktop/ic_test$ openroad -no_init\r\nOpenROAD v2.0-6895-g5c85b36f8 \r\nThis program is licensed under the BSD-3 license. See the LICENSE file for details.\r\nComponents of this program may be licensed under more restrictive licenses which must be honored.\r\nopenroad> \r\nopenroad> read_design -json and_gate.json\r\ninvalid command name \"read_design\"\r\nwhile evaluating read_design -json and_gate.json\r\nopenroad> \r\nopenroad> read_verilog and_gate.v\r\n[ERROR STA-0164] and_gate.v line 2, syntax error\r\nSTA-0164\r\nwhile evaluating read_verilog and_gate.v\r\nopenroad> \r\nopenroad>\r\n```\r\n\r\nThis is `openroad help` in my machine\r\nClick here to see details
\r\n\r\n```json\r\n{\r\n \"creator\": \"Yosys 0.13+15 (git sha1 bc027b2ca, gcc 11.3.0-1ubuntu1~22.04 -fPIC -Os)\",\r\n \"modules\": {\r\n \"and_gate\": {\r\n \"attributes\": {\r\n \"top\": \"00000000000000000000000000000001\",\r\n \"src\": \"and_gate.v:1.1-3.10\"\r\n },\r\n \"ports\": {\r\n \"a\": {\r\n \"direction\": \"input\",\r\n \"bits\": [ 2 ]\r\n },\r\n \"b\": {\r\n \"direction\": \"input\",\r\n \"bits\": [ 3 ]\r\n },\r\n \"c\": {\r\n \"direction\": \"output\",\r\n \"bits\": [ 4 ]\r\n }\r\n },\r\n \"cells\": {\r\n \"$abc$76$auto$blifparse.cc:381:parse_blif$77\": {\r\n \"hide_name\": 1,\r\n \"type\": \"$_AND_\",\r\n \"parameters\": {\r\n },\r\n \"attributes\": {\r\n },\r\n \"port_directions\": {\r\n \"A\": \"input\",\r\n \"B\": \"input\",\r\n \"Y\": \"output\"\r\n },\r\n \"connections\": {\r\n \"A\": [ 3 ],\r\n \"B\": [ 2 ],\r\n \"Y\": [ 4 ]\r\n }\r\n }\r\n },\r\n \"netnames\": {\r\n \"a\": {\r\n \"hide_name\": 0,\r\n \"bits\": [ 2 ],\r\n \"attributes\": {\r\n \"src\": \"and_gate.v:1.23-1.24\"\r\n }\r\n },\r\n \"b\": {\r\n \"hide_name\": 0,\r\n \"bits\": [ 3 ],\r\n \"attributes\": {\r\n \"src\": \"and_gate.v:1.32-1.33\"\r\n }\r\n },\r\n \"c\": {\r\n \"hide_name\": 0,\r\n \"bits\": [ 4 ],\r\n \"attributes\": {\r\n \"src\": \"and_gate.v:1.42-1.43\"\r\n }\r\n }\r\n }\r\n }\r\n }\r\n}\r\n```\r\n\r\n] [-macro] [-existing]\r\n [-grid_over_pg_pins|-grid_over_boundary]\r\n [-voltage_domains ]\r\n [-orient ] [-instances ]\r\n [-cells ] [-default] [-halo ]\r\n [-pins ] [-starts_with (POWER|GROUND)]\r\n [-obstructions ] [-power_switch_cell ]\r\n [-power_control ] [-power_control_network (STAR|DAISY)]\r\ndefine_pin_shape_pattern [-layer layer] [-x_step x_step] [-y_step y_step]\r\n [-region region] [-size size] [-pin_keepout dist]\r\ndefine_power_switch_cell -name\r\ndefine_process_corner [-ext_model_index index] filename\r\ndelete_clock [-all] clocks\r\ndelete_from_list list objs\r\ndelete_generated_clock [-all] clocks\r\ndelete_instance inst\r\ndelete_net net\r\ndelete_physical_cluster cluster_name\r\ndelete_voltage_domain domain_name\r\ndensity_fill [-rules rules_file] [-area {lx ly ux uy}]\r\ndetailed_placement [-max_displacement disp|{disp_x disp_y}]\r\ndetailed_route [-output_maze filename] [-output_drc filename]\r\n [-output_cmap filename] [-output_guide_coverage filename]\r\n [-db_process_node name] [-disable_via_gen] [-droute_end_iter iter]\r\n [-via_in_pin_bottom_layer layer] [-via_in_pin_top_layer layer]\r\n [-or_seed seed] [-or_k_ k] [-bottom_routing_layer layer]\r\n [-top_routing_layer layer] [-verbose level] [-param filename] [-distributed]\r\n [-remote_host rhost] [-remote_port rport] [-shared_volume vol]\r\n [-cloud_size sz] [-clean_patches] [-no_pin_access] [-min_access_points count]\r\n [-save_guide_updates] [-repair_pdn_vias layer]\r\ndetailed_route_debug [-pa] [-ta] [-dr] [-maze] [-net name] [-pin name]\r\n [-worker x y] [-iter iter] [-pa_markers] [-dump_dr] [-dump_dir dir]\r\n [-pa_edge] [-pa_commit]\r\ndetailed_route_run_worker [-dump_dir dir] [-worker_dir dir] [-drc_rpt drc]\r\ndetailed_route_worker_debug [-maze_end_iter iter] [-drc_cost d_cost]\r\n [-marker_cost m_cost] [-fixed_shape_cost f_cost] [-marker_decay m_decay]\r\n [-ripup_mode mode] [-follow_guide f_guide]\r\ndiff_spef [-file filename] [-r_res] [-r_cap] [-r_cc_cap] [-r_conn]\r\ndisconnect_pin net -all|pin\r\ndisconnect_pins net -all|pins\r\ndisplay_timing_cone pin [-fanin] [-fanout] [-off]\r\ndraw_route_guides net_names [-show_pin_locations]\r\nelapsed_run_time\r\nestimate_parasitics -placement|-global_routing\r\nextract_parasitics [-ext_model_file filename] [-corner_cnt count]\r\n [-max_res ohms] [-coupling_threshold fF] [-debug_net_id id] [-lef_res]\r\n [-cc_model track] [-context_depth depth] [-no_merge_via_res]\r\nfiller_placement [-prefix prefix] filler_masters\r\nfind_timing_paths [-from from_list|-rise_from from_list|-fall_from from_list]\r\n [-through through_list|-rise_through through_list|-fall_through through_list]\r\n [-to to_list|-rise_to to_list|-fall_to to_list]\r\n [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max]\r\n [-unconstrained] [-corner corner] [-group_count path_count]\r\n [-endpoint_count path_count] [-unique_paths_to_endpoint]\r\n [-slack_max slack_max] [-slack_min slack_min] [-sort_by_slack]\r\n [-path_group group_name]\r\nfocus_net net [-remove] [-clear]\r\nget_cells [-hierarchical] [-hsc separator] [-filter expr] [-regexp] [-nocase]\r\n [-quiet] [-of_objects objects] [patterns]\r\nget_clocks [-regexp] [-nocase] [-quiet] patterns\r\nget_fanin -to sink_list [-flat] [-only_cells] [-startpoints_only]\r\n [-levels level_count] [-pin_levels pin_count]\r\n [-trace_arcs timing|enabled|all]\r\nget_fanout -from source_list [-flat] [-only_cells] [-endpoints_only]\r\n [-levels level_count] [-pin_levels pin_count]\r\n [-trace_arcs timing|enabled|all]\r\nget_full_name objects\r\nget_lib_cells [-hsc separator] [-regexp] [-nocase] [-quiet]\r\n [-of_objects objects] [patterns]\r\nget_lib_pins [-hsc separator] [-regexp] [-nocase] [-quiet] patterns\r\nget_libs [-regexp] [-nocase] [-quiet] patterns\r\nget_name objects\r\nget_nets [-hierarchical] [-hsc separator] [-regexp] [-nocase] [-quiet]\r\n [-of_objects objects] [patterns]\r\nget_pins [-hierarchical] [-hsc separator] [-quiet] [-filter expr] [-regexp]\r\n [-nocase] [-of_objects objects] patterns\r\nget_ports [-quiet] [-filter expr] [-regexp] [-nocase] [-of_objects objects]\r\n [patterns]\r\nget_property [-object_type cell|pin|net|port|clock|timing_arc] object property\r\nget_timing_edges [-from from_pin] [-to to_pin] [-of_objects objects]\r\n [-filter expr]\r\nglobal_connect\r\nglobal_placement [-skip_initial_place] [-skip_nesterov_place] [-timing_driven]\r\n [-routability_driven] [-disable_timing_driven] [-disable_routability_driven]\r\n [-incremental] [-force_cpu] [-skip_io] [-bin_grid_count grid_count]\r\n [-density target_density] [-init_density_penalty init_density_penalty]\r\n [-init_wirelength_coef init_wirelength_coef] [-min_phi_coef min_phi_coef]\r\n [-max_phi_coef max_phi_coef] [-reference_hpwl reference_hpwl]\r\n [-overflow overflow] [-initial_place_max_iter initial_place_max_iter]\r\n [-initial_place_max_fanout initial_place_max_fanout]\r\n [-routability_check_overflow routability_check_overflow]\r\n [-routability_max_density routability_max_density]\r\n [-routability_max_bloat_iter routability_max_bloat_iter]\r\n [-routability_max_inflation_iter routability_max_inflation_iter]\r\n [-routability_target_rc_metric routability_target_rc_metric]\r\n [-routability_inflation_ratio_coef routability_inflation_ratio_coef]\r\n [-routability_max_inflation_ratio routability_max_inflation_ratio]\r\n [-routability_rc_coefficients routability_rc_coefficients]\r\n [-timing_driven_net_reweight_overflow timing_driven_net_reweight_overflow]\r\n [-timing_driven_net_weight_max timing_driven_net_weight_max]\r\n [-timing_driven_nets_percentage timing_driven_nets_percentage]\r\n [-pad_left pad_left] [-pad_right pad_right]\r\nglobal_route [-guide_file out_file] [-congestion_iterations iterations]\r\n [-congestion_report_file file_name] [-grid_origin origin]\r\n [-overflow_iterations iterations] [-critical_nets_percentage percent]\r\n [-allow_congestion] [-allow_overflow] [-verbose]\r\nglobal_route_debug [-st]\r\ngroup_path -name group_name [-weight weight] [-critical_range range] [-default]\r\n [-comment comment] [-from from_list] [-rise_from from_list]\r\n [-fall_from from_list] [-through through_list] [-rise_through through_list]\r\n [-fall_through through_list] [-to to_list] [-rise_to to_list]\r\n [-fall_to to_list]\r\nhelp [pattern]\r\nhighlight_path [-min|-max] pin\r\nimprove_placement [-random_seed seed] [-max_displacement disp|{disp_x disp_y}]\r\ninitialize_floorplan [-utilization util] [-aspect_ratio ratio]\r\n [-core_space space | {bottom top left right}] [-die_area {lx ly ux uy}]\r\n [-core_area {lx ly ux uy}] [-site site_name]\r\ninitialize_padring [-signal_assignment_file signal_assigment_file]\r\ninsert_buffer buffer_name buffer_cell net load_pins buffer_out_net_name\r\ninsert_tiecells tie_pin [-prefix prefix]\r\nlink_design [top_cell_name]\r\nlog_begin filename\r\nlog_end\r\nmacro_placement [-halo {vertical_width horizontal_width}]\r\n [-channel {vertical_width horizontal_width}] [-fence_region {lx ly ux uy}]\r\n [-snap_layer snap_layer_number] [-style corner_max_wl|corner_min_wl]\r\nmacro_placement_debug [-partitions]\r\nmake_instance inst_path lib_cell\r\nmake_net\r\nmake_tracks [layer] [-x_pitch x_pitch] [-y_pitch y_pitch] [-x_offset x_offset]\r\n [-y_offset y_offset]\r\noptimize_mirroring\r\npdngen [-skip_trim] [-dont_add_pins] [-reset] [-ripup] [-report_only]\r\n [-failed_via_report file]\r\npin_access [-db_process_node name] [-bottom_routing_layer layer]\r\n [-top_routing_layer layer] [-min_access_points count] [-verbose level]\r\nplace_cell -inst_name inst_name [-cell library_cell] -origin xy_origin -orient\r\nplace_pin [-pin_name pin_name] [-layer layer] [-location location]\r\n [-pin_size pin_size] [-force_to_die_boundary]\r\nplace_pins [-hor_layers h_layers] [-ver_layers v_layers] [-random_seed seed]\r\n [-random] [-corner_avoidance distance] [-min_distance min_dist]\r\n [-min_distance_in_tracks] [-exclude region] [-group_pins pin_list]\r\nread_db filename\r\nread_def [-floorplan_initialize|-incremental] [-continue_on_errors] filename\r\nread_guides file_name\r\nread_lef [-tech] [-library] filename\r\nread_liberty [-corner corner] [-min] [-max] [-no_latch_infer] filename\r\nread_parasitics [-min] [-max] [-elmore] [-path path] [-increment]\r\n [-pin_cap_included] [-keep_capacitive_coupling]\r\n [-coupling_reduction_factor factor] [-reduce_to pi_elmore|pi_pole_residue2]\r\n [-delete_after_reduce] [-quiet] [-save] filename\r\nread_power_activities [-scope scope] -vcd filename\r\nread_sdc [-echo] filename\r\nread_sdf [-path path] [-corner corner] [-cond_use min|max|min_max]\r\n [-unescaped_dividers] filename\r\nread_spef [-corner corner] [-min] [-max] [-path path] [-pin_cap_included]\r\n [-keep_capacitive_coupling] [-coupling_reduction_factor factor]\r\n [-reduce_to pi_elmore|pi_pole_residue2] [-delete_after_reduce] [-quiet]\r\n [-save] filename\r\nread_upf [-file file]\r\nread_verilog filename\r\nremove_buffers\r\nremove_fillers\r\nremove_from_physical_cluster\r\n [-parent_module module_name -modinst modinst_name | -inst inst_name | -physical_cluster cluster_name]\r\n cluster_name\r\nrepair_antennas [diode_cell/diode_port] [-iterations iterations]\r\n [-ratio_margin ratio_margin]\r\nrepair_clock_inverters\r\nrepair_clock_nets [-max_wire_length max_wire_length]\r\nrepair_design [-max_wire_length max_wire_length] [-max_utilization util]\r\n [-slew_margin slack_margin] [-cap_margin cap_margin]\r\nrepair_pdn_vias [-net net_name] -all\r\nrepair_tie_fanout lib_port [-separation dist] [-verbose]\r\nrepair_timing [-setup] [-hold] [-setup_margin setup_margin]\r\n [-hold_margin hold_margin] [-allow_setup_violations]\r\n [-repair_tns tns_end_percent] [-max_buffer_percent buffer_percent]\r\n [-max_utilization util]\r\nreplace_cell instance lib_cell\r\nreport_annotated_check [-setup] [-hold] [-recovery] [-removal] [-nochange]\r\n [-width] [-period] [-max_skew] [-max_line lines] [-list_annotated]\r\n [-list_not_annotated] [-constant_arcs]\r\nreport_annotated_delay [-cell] [-net] [-from_in_ports] [-to_out_ports]\r\n [-max_line lines] [-list_annotated] [-list_not_annotated] [-constant_arcs]\r\nreport_arrival pin\r\nreport_cell [-connections] [-verbose] instance_path [> filename] [>> filename]\r\nreport_check_types [-violators] [-verbose] [-corner corner]\r\n [-format slack_only|end] [-max_delay] [-min_delay] [-recovery] [-removal]\r\n [-clock_gating_setup] [-clock_gating_hold] [-max_slew] [-min_slew]\r\n [-max_fanout] [-min_fanout] [-max_capacitance] [-min_capacitance]\r\n [-min_pulse_width] [-min_period] [-max_skew] [-net net] [-digits digits]\r\n [-no_line_splits] [> filename] [>> filename]\r\nreport_checks [-from from_list|-rise_from from_list|-fall_from from_list]\r\n [-through through_list|-rise_through through_list|-fall_through through_list]\r\n [-to to_list|-rise_to to_list|-fall_to to_list] [-unconstrained]\r\n [-path_delay min|min_rise|min_fall|max|max_rise|max_fall|min_max]\r\n [-corner corner] [-group_count path_count] [-endpoint_count path_count]\r\n [-unique_paths_to_endpoint] [-slack_max slack_max] [-slack_min slack_min]\r\n [-sort_by_slack] [-path_group group_name]\r\n [-format full|full_clock|full_clock_expanded|short|end|summary]\r\nreport_clock_min_period [-clocks clocks] [-include_port_paths]\r\nreport_clock_properties [clocks]\r\nreport_clock_skew [-setup|-hold] [-clock clocks] [-corner corner]]\r\n [-digits digits]\r\nreport_clock_skew_metric [-setup] | [-hold]\r\nreport_constant pin|instance|net\r\nreport_cts [-out_file file]\r\nreport_dcalc [-from from_pin] [-to to_pin] [-corner corner] [-min] [-max]\r\n [-digits digits]\r\nreport_design_area\r\nreport_design_area_metrics\r\nreport_disabled_edges\r\nreport_edges [-from from_pin] [-to to_pin]\r\nreport_erc_metrics\r\nreport_floating_nets [-verbose]\r\nreport_global_connect\r\nreport_instance [-connections] [-verbose] instance_path [> filename]\r\n [>> filename]\r\nreport_lib_cell cell_name [> filename] [>> filename]\r\nreport_long_wires count\r\nreport_net [-connections] [-verbose] [-corner corner] [-digits digits]\r\n [-hier_pins] net_path [> filename] [>> filename]\r\nreport_object_full_names objects\r\nreport_object_names objects\r\nreport_parasitic_annotation -report_unannotated\r\nreport_path [-min|-max]\r\n [-format full|full_clock|full_clock_expanded|short|end|summary]\r\nreport_physical_clusters\r\nreport_pin [-corner corner] [-digits digits] pin [> filename] [>> filename]\r\nreport_power [-instances instances] [-corner corner] [-digits digits]\r\n [> filename] [>> filename]\r\nreport_power_metric [-corner corner_name]\r\nreport_pulse_width_checks [-verbose] [-corner corner] [-digits digits]\r\n [-no_line_splits] [pins] [> filename] [>> filename]\r\nreport_required pin\r\nreport_slack pin\r\nreport_slews [-corner corner] pin\r\nreport_tns [-digits digits]\r\nreport_tns_metric [-setup] | [-hold]\r\nreport_units\r\nreport_units_metric\r\nreport_voltage_domains\r\nreport_wire_length [-net net_list] [-file file] [-global_route]\r\n [-detailed_route] [-verbose]\r\nreport_wns [-digits digits]\r\nreport_worst_negative_slack_metric [-setup] | [-hold]\r\nreport_worst_slack [-min] [-max] [-digits digits]\r\nreport_worst_slack_metric [-setup] | [-hold]\r\nrestructure [-slack_threshold slack] [-depth_threshold depth]\r\n [-target area|timing] [-liberty_file liberty_file] [-tielo_port tielow_port]\r\n [-tiehi_port tiehigh_port] [-work_dir workdir_name]\r\nrtl_macro_placer -max_num_macro max_num_macro -min_num_macro min_num_macro\r\n -max_num_inst max_num_inst -min_num_inst min_num_inst -tolerance tolerance\r\n -max_num_level max_num_level -coarsening_ratio coarsening_ratio\r\n -num_bundled_ios num_bundled_ios -large_net_threshold large_net_threshold\r\n -signature_net_threshold signature_net_threshold -halo_width halo_width\r\n -fence_lx fence_lx -fence_ly fence_ly -fence_ux fence_ux -fence_uy fence_uy\r\n -area_weight area_weight -outline_weight outline_weight -wirelength_weight\r\n wirelength_weight -guidance_weight guidance_weight -fence_weight fence_weight\r\n -boundary_weight boundary_weight -notch_weight notch_weight\r\n -macro_blockage_weight macro_blockage_weight -pin_access_th pin_access_th\r\n -target_util target_util -target_dead_space target_dead_space -min_ar min_ar\r\n -snap_layer snap_layer -report_directory report_directory\r\nrun_load_balancer [-host host] [-port port] [-workers_domain workers_domain]\r\nrun_worker [-host host] [-port port] [-i]\r\nsave_image [-area {x0 y0 x1 y1}] [-resolution microns_per_pixel]\r\n [-display_option option] path\r\nselect -type object_type [-name name_regex] [-case_insensitive]\r\n [-highlight group]\r\nset_assigned_check -setup|-hold|-recovery|-removal [-rise] [-fall]\r\n [-corner corner] [-min] [-max] [-from from_pins] [-to to_pins]\r\n [-clock rise|fall] [-cond sdf_cond] check_value\r\nset_assigned_delay -cell|-net [-rise] [-fall] [-corner corner] [-min] [-max]\r\n [-from from_pins] [-to to_pins] delay\r\nset_assigned_transition [-rise] [-fall] [-corner corner] [-min] [-max] slew pins\r\nset_bump -row row -col col [(-power|-ground|-net) net_name] [-remove]\r\nset_bump_options [-pitch pitch] [-bump_pin_name pin_name]\r\n [-spacing_to_edge spacing] [-offset {x_offset y_offset}]\r\n [-array_size {rows columns}] [-cell_name bump_cell_table]\r\n [-num_pads_per_tile value] [-rdl_layer name] [-rdl_width value]\r\n [-rdl_spacing value] [-rdl_route_style (45|90|under)]\r\n [-padcell_to_rdl list_of_vias] [-rdl_to_bump list_of_vias]\r\n [-rdl_cover_file_name rdl_file_name]\r\nset_case_analysis 0|1|zero|one|rise|rising|fall|falling pins\r\nset_clock_gating_check [-setup setup_time] [-hold hold_time] [-rise] [-fall]\r\n [-low] [-high] [objects]\r\nset_clock_groups [-name name] [-logically_exclusive] [-physically_exclusive]\r\n [-asynchronous] [-allow_paths] [-comment comment] -group clocks\r\nset_clock_latency [-source] [-clock clock] [-rise] [-fall] [-min] [-max]\r\n [-early] [-late] delay objects\r\nset_clock_sense [-positive] [-negative] [-pulse pulse_type] [-stop_propagation]\r\n [-clock clocks] pins\r\nset_clock_transition [-rise] [-fall] [-min] [-max] transition clocks\r\nset_clock_uncertainty [-from|-rise_from|-fall_from from_clock]\r\n [-to|-rise_to|-fall_to to_clock] [-rise] [-fall] [-setup] [-hold] uncertainty\r\n [objects]\r\nset_cmd_units [-capacitance cap_unit] [-resistance res_unit] [-time time_unit]\r\n [-voltage voltage_unit] [-current current_unit] [-power power_unit]\r\n [-distance distance_unit]\r\nset_data_check [-from from_pin] [-rise_from from_pin] [-fall_from from_pin]\r\n [-to to_pin] [-rise_to to_pin] [-fall_to to_pin] [-setup | -hold]\r\n [-clock clock] margin\r\nset_debug_level tool group level\r\nset_disable_inferred_clock_gating objects\r\nset_disable_timing [-from from_port] [-to to_port] objects\r\nset_domain_area domain_name -area\r\nset_dont_touch nets_instances\r\nset_dont_use lib_cells\r\nset_drive [-rise] [-fall] [-min] [-max] resistance ports\r\nset_driving_cell [-lib_cell cell] [-library library] [-rise] [-fall] [-min]\r\n [-max] [-pin pin] [-from_pin from_pin] [-input_transition_rise trans_rise]\r\n [-input_transition_fall trans_fall] [-multiply_by factor] [-dont_scale]\r\n [-no_design_rule] ports\r\nset_false_path [-setup] [-hold] [-rise] [-fall] [-reset_path] [-comment comment]\r\n [-from from_list] [-rise_from from_list] [-fall_from from_list]\r\n [-through through_list] [-rise_through through_list]\r\n [-fall_through through_list] [-to to_list] [-rise_to to_list]\r\n [-fall_to to_list]\r\nset_fanout_load fanout ports\r\nset_global_routing_layer_adjustment layer adj\r\nset_global_routing_random [-seed seed]\r\n [-capacities_perturbation_percentage percent] [-perturbation_amount value]\r\nset_global_routing_region_adjustment region [-layer layer]\r\n [-adjustment adjustment]\r\nset_hierarchy_separator seperator\r\nset_ideal_latency [-rise] [-fall] [-min] [-max] delay objects\r\nset_ideal_net nets\r\nset_ideal_network [-no_propagation] objects\r\nset_ideal_transition [-rise] [-fall] [-min] [-max] transition_time objects\r\nset_input_delay [-rise] [-fall] [-max] [-min] [-clock clock] [-clock_fall]\r\n [-reference_pin ref_pin] [-source_latency_included]\r\n [-network_latency_included] [-add_delay] delay port_pin_list\r\nset_input_transition [-rise] [-fall] [-min] [-max] transition ports\r\nset_io_pin_constraint [-direction direction] [-pin_names names] [-region region]\r\n [-mirrored_pins pins]\r\nset_isolation [-domain domain] [-applies_to applies_to]\r\n [-clamp_value clamp_value] [-isolation_signal isolation_signal]\r\n [-isolation_sense isolation_sense] [-location location] [-update] name\r\nset_layer_rc [-layer layer] [-via via_layer] [-capacitance cap]\r\n [-resistance res] [-corner corner]\r\nset_level_shifter_strategy [-rule rule_type]\r\nset_level_shifter_threshold [-voltage volt]\r\nset_load [-rise] [-fall] [-max] [-min] [-subtract_pin_load] [-pin_load]\r\n [-wire_load] capacitance objects\r\nset_logic_dc port_list\r\nset_logic_one port_list\r\nset_logic_zero port_list\r\nset_macro_extension extension\r\nset_max_area area\r\nset_max_capacitance cap objects\r\nset_max_delay [-rise] [-fall] [-ignore_clock_latency] [-reset_path]\r\n [-comment comment] [-from from_list] [-rise_from from_list]\r\n [-fall_from from_list] [-through through_list] [-rise_through through_list]\r\n [-fall_through through_list] [-to to_list] [-rise_to to_list]\r\n [-fall_to to_list] delay\r\nset_max_dynamic_power power [unit]\r\nset_max_fanout fanout objects\r\nset_max_leakage_power power [unit]\r\nset_max_time_borrow limit objects\r\nset_max_transition [-clock_path] [-data_path] [-rise] [-fall] slew objects\r\nset_min_capacitance cap objects\r\nset_min_delay [-rise] [-fall] [-ignore_clock_latency] [-reset_path]\r\n [-comment comment] [-from from_list] [-rise_from from_list]\r\n [-fall_from from_list] [-through through_list] [-rise_through through_list]\r\n [-fall_through through_list] [-to to_list] [-rise_to to_list]\r\n [-fall_to to_list] delay\r\nset_min_pulse_width [-low] [-high] value [objects]\r\nset_multicycle_path [-setup] [-hold] [-rise] [-fall] [-start] [-end]\r\n [-reset_path] [-comment comment] [-from from_list] [-rise_from from_list]\r\n [-fall_from from_list] [-through through_list] [-rise_through through_list]\r\n [-fall_through through_list] [-to to_list] [-rise_to to_list]\r\n [-fall_to to_list] path_multiplier\r\nset_operating_conditions [-analysis_type single|bc_wc|on_chip_variation]\r\n [-library lib] [condition] [-min min_condition] [-max max_condition]\r\n [-min_library min_lib] [-max_library max_lib]\r\nset_output_delay [-rise] [-fall] [-max] [-min] [-clock clock] [-clock_fall]\r\n [-reference_pin ref_pin] [-source_latency_included]\r\n [-network_latency_included] [-add_delay] delay port_pin_list\r\nset_padring_options [-type (flipchip|wirebond)] [-power power_nets]\r\n [-ground ground_nets] [-core_area core_area] [-die_area die_area]\r\n [-offsets offsets] [-pad_inst_pattern pad_inst_pattern]\r\n [-pad_pin_pattern pad_pin_pattern] [-pad_pin_layer pin_layer_name]\r\n [-pin_layer layer_name] [-connect_by_abutment signal_list]\r\n [-allow_filler_overlap]\r\nset_pdnsim_net_voltage [-net net_name] [-voltage volt]\r\nset_pin_length [-hor_length h_length] [-ver_length v_length]\r\nset_pin_length_extension [-hor_extension h_ext] [-ver_extension v_ext]\r\nset_pin_offset offset\r\nset_pin_thick_multiplier [-hor_multiplier h_mult] [-ver_multiplier v_mult]\r\nset_placement_padding -global|-masters masters|-instances insts\r\n [-right site_count] [-left site_count] [instances]\r\nset_pocv_sigma_factor factor\r\nset_port_fanout_number [-max] [-min] fanout ports\r\nset_power_activity [-global] [-input] [-input_ports ports] [-pins pins]\r\n [-activity activity] [-duty duty]\r\nset_propagated_clock objects\r\nset_pvt insts [-min] [-max] [-process process] [-voltage voltage]\r\n [-temperature temperature]\r\nset_resistance [-min] [-max] resistance nets\r\nset_routing_alpha alpha [-net net_name] [-min_fanout fanout] [-min_hpwl hpwl]\r\n [-clock_nets]\r\nset_routing_layers [-signal layers] [-clock layers]\r\nset_sense [-type clock|data] [-positive] [-negative] [-pulse pulse_type]\r\n [-stop_propagation] [-clocks clocks] pins\r\nset_timing_derate -early|-late [-rise] [-fall] [-clock] [-data] [-net_delay]\r\n [-cell_delay] [-cell_check] derate [objects]\r\nset_units [-time time_unit] [-capacitance cap_unit] [-resistance res_unit]\r\n [-voltage voltage_unit] [-current current_unit] [-power power_unit]\r\n [-distance distance_unit]\r\nset_voltage_domain -name domain_name -power power_net_name -ground\r\n ground_net_name [-region region_name]\r\n [-secondary_power secondary_power_net_name]\r\n [-switched_power switched_power_net_name]\r\nset_wire_load_min_block_size block_size\r\nset_wire_load_mode top|enclosed|segmented\r\nset_wire_load_model -name model_name [-library lib_name] [-min] [-max] [objects]\r\nset_wire_load_selection_group [-library lib] [-min] [-max] group_name [objects]\r\nset_wire_rc [-clock] [-signal] [-layer layer_name] [-resistance res]\r\n [-capacitance cap] [-corner corner]\r\nshow_copying\r\nshow_splash\r\nshow_warranty\r\nsource [-echo] [-verbose] filename [> filename] [>> filename]\r\nsuppress_message tool id\r\ntapcell [-tapcell_master tapcell_master] [-tap_prefix tap_prefix]\r\n [-endcap_master endcap_master] [-endcap_cpp endcap_cpp]\r\n [-endcap_prefix endcap_prefix] [-distance dist] [-halo_width_x halo_x]\r\n [-halo_width_y halo_y] [-tap_nwin2_master tap_nwin2_master]\r\n [-tap_nwin3_master tap_nwin3_master] [-tap_nwout2_master tap_nwout2_master]\r\n [-tap_nwout3_master tap_nwout3_master]\r\n [-tap_nwintie_master tap_nwintie_master]\r\n [-tap_nwouttie_master tap_nwouttie_master]\r\n [-cnrcap_nwin_master cnrcap_nwin_master]\r\n [-cnrcap_nwout_master cnrcap_nwout_master]\r\n [-incnrcap_nwin_master incnrcap_nwin_master]\r\n [-incnrcap_nwout_master incnrcap_nwout_master] [-tbtie_cpp tbtie_cpp]\r\n [-no_cell_at_top_bottom]\r\ntapcell_ripup [-tap_prefix tap_prefix] [-endcap_prefix endcap_prefix]\r\ntriton_part_design [-num_parts num_parts]\r\n [-balance_constraint balance_constraint] [-seed seed]\r\n [-solution_file file_name] [-paths_file file_name]\r\n [-hypergraph_file file_name]\r\ntriton_part_hypergraph -hypergraph_file hypergraph_file [-fixed_file fixed_file]\r\n [-num_parts num_parts] [-balance_constraint balance_constraint]\r\n [-vertex_dimension vertex_dimension]\r\n [-hyperedge_dimension hyperedge_dimension] [-seed seed]\r\nunset_case_analysis pins\r\nunset_clock_groups [-logically_exclusive] [-physically_exclusive]\r\n [-asynchronous] [-name names] [-all]\r\nunset_clock_latency [-source] [-clock clock] objects\r\nunset_clock_transition clocks\r\nunset_clock_uncertainty [-from|-rise_from|-fall_from from_clock]\r\n [-to|-rise_to|-fall_to to_clock] [-rise] [-fall] [-setup] [-hold] [objects]\r\nunset_data_check [-from from_pin] [-rise_from from_pin] [-fall_from from_pin]\r\n [-to to_pin] [-rise_to to_pin] [-fall_to to_pin] [-setup | -hold]\r\n [-clock clock]\r\nunset_disable_inferred_clock_gating objects\r\nunset_disable_timing [-from from_port] [-to to_port] objects\r\nunset_dont_touch nets_instances\r\nunset_dont_use lib_cells\r\nunset_generated_clock [-all] clocks\r\nunset_input_delay [-rise] [-fall] [-max] [-min] [-clock clock] [-clock_fall]\r\n port_pin_list\r\nunset_output_delay [-rise] [-fall] [-max] [-min] [-clock clock] [-clock_fall]\r\n port_pin_list\r\nunset_path_exceptions [-setup] [-hold] [-rise] [-fall] [-from from_list]\r\n [-rise_from from_list] [-fall_from from_list] [-through through_list]\r\n [-rise_through through_list] [-fall_through through_list] [-to to_list]\r\n [-rise_to to_list] [-fall_to to_list]\r\nunset_propagated_clock objects\r\nunset_timing_derate\r\nuse_interface_cell [-domain domain] [-strategy strategy] [-lib_cells lib_cells]\r\nuser_run_time\r\nwith_output_to_variable var\r\nwrite_abstract_lef [-bloat_factor amount|-bloat_occupied_layers] filename\r\nwrite_cdl [-include_fillers] -masters masters_filenames out_filename\r\nwrite_db filename\r\nwrite_def [-version version] filename\r\nwrite_guides filename\r\nwrite_lef filename\r\nwrite_path_spice -path_args path_args -spice_directory spice_directory\r\n -lib_subckt_file lib_subckts_file -model_file model_file -power power -ground\r\n ground\r\nwrite_pg_spice [-vsrc vsrc_file ] [-outfile out_file] [-net net_name]\r\n [-dx bump_pitch_x] [-dy bump_pitch_y]\r\nwrite_rules [-file filename] [-dir dir] [-name name] [-pattern pattern]\r\nwrite_sdc [-map_hpins] [-digits digits] [-gzip] [-no_timestamp] filename\r\nwrite_sdf [-corner corner] [-divider /|.] [-include_typ] [-digits digits]\r\n [-gzip] [-no_timestamp] [-no_version] filename\r\nwrite_spef [-net_id net_id] [-nets nets] filename\r\nwrite_timing_model [-corner corner] [-library_name lib_name]\r\n [-cell_name cell_name] filename\r\nwrite_verilog [-sort] [-include_pwr_gnd] [-remove_cells cells] filename\r\nopenroad>\r\n```\r\n
\r\n\r\n---\r\nThank you so much,\r\nVic P."}, {"assistant": "1. OpenROAD only supports verilog netlists.\r\n2. Your SDC file mentions a clock that does not exist. You have `[get_ports clk]` but there is no `clk` input in your design.\r\n\r\nYou should probably be using [OpenROAD Flow Scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts) to run a flow instead of manually running yosys."}]}
+{"messages": [{"user": "I was running the riscv model with default setup. When I was trying to find wns for hold after the full run (or in cts, route). It is returning as INF.\r\n\r\nCommand:\r\n```\r\nreport_worst_slack -min\r\n```\r\nReturns `worst slack INF`\r\n\r\n**pdk:** asap7\r\n**design:** riscv32i\r\n\r\nAny idea why is that and how to solve it?"}, {"assistant": "In which PDK? How did you load the design? Please give specific steps to reproduce the issue."}, {"assistant": "I guess you meant ```make gui_6_final.odb``` without the 'e'. I get:\r\n\r\n```\r\n>>> report_worst_slack -min\r\nworst slack 40.29\r\n```\r\n\r\nWhat commit id are you using for OR & ORFS? This would have worked better as an issue with the required info."}]}
+{"messages": [{"user": "Hi OpenRoad devs,\r\n\r\nPart of the scan architect step (to create the scan chains) is to see what clock is driving each one of the cells of the design. I was wondering: what is the best way in OpenRoad to find out what is the clock driver and the edge (Rising or Falling) of a given cell?.\r\n\r\nI can always traverse back the nets from a clock pin but maybe there is already some infra that I can use for this.\r\n\r\nThanks!,\r\nFelipe"}, {"assistant": "I think Sta::clocks(const Pin *pin) is what you want."}]}
+{"messages": [{"user": "I was successfully able to run cmake and then make. However, output of cmake has following two messages which seems problematic to me. How do I resolve these?\r\n\r\n-- GUI is not enabled\r\n-- Could NOT find VTune (missing: VTune_LIBRARIES VTune_INCLUDE_DIRS)\r\n\r\nI ran following command\r\ncmake .. -DCMAKE_INSTALL_PREFIX=/home/msingh/openRoad -DPYTHON_INCLUDE_DIR=$(python3 -c \"import sysconfig; print(sysconfig.get_path('include'))\") -DPYTHON_LIBRARY=$(python3 -c\\\r\n \"import sysconfig; print(sysconfig.get_config_var('LIBDIR'))\")\r\n\r\nI also ran make afterwards, which seems to finish. There are bunch of warnings but no error message. Where do I find the executable. I don't find it in CMAKE_INSTALL_PREFIX/bin directory.\r\n\r\nDoes it mean that installation didn't complete? \r\n\r\nI am looking for some help because I am stuck in the installation.\r\n\r\nI just cleared the buffer that has log, but I can redo those steps if you need the complete log output."}, {"assistant": "Vtune is unimportant unless you are a developer of OR.\r\n\r\nThe GUI suggests that you don't have Qt installed. Did you run the dependency installer?"}, {"user": "Thanks Maliberty for response.\r\n\r\nI followed the steps \"https://openroad-flow-scripts.readthedocs.io/en/latest/user/BuildLocally.html\" and was able to build with hiccups. \r\nHow do I make sure Qt is installed? BTW - I am trying to install it on Linux RH8. Is it supported platform?\r\n\r\nWhen I try to invoke it, I get this missing library error.\r\nopenroad -help\r\nopenroad: error while loading shared libraries: libortools.so.9: cannot open shared object file: No such file or directory\r\n"}, {"assistant": "I don't know what OS you are on and you haven't included any logs. If you look at https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/etc/DependencyInstaller.sh it you'll see it references Qt libraries."}, {"user": "I am trying to build it on RH8. I am really stuck at this point now. I ran \"sudo ./DependencyInstaller.sh\" successfully. \r\n\r\nI can check that qt5 is installed.\r\n\r\n[msingh@lnx-msingh cv6 /tmp]$ sudo yum -y install qt5-srpm-macros.noarch\r\nLast metadata expiration check: 0:07:51 ago on Sun 12 Mar 2023 12:19:34 AM PST.\r\nPackage qt5-srpm-macros-5.12.5-3.el8.noarch is already installed.\r\nDependencies resolved.\r\nNothing to do.\r\n\r\nWhen I run cmake to create build files, I get that \"GUI is not enabled\". Is there a switch I need to pass to cmake. Here is my command and it's output.\r\n\r\n[msingh@lnx-msingh cv6 build]$ cmake .. -DPYTHON_INCLUDE_DIR=/cv6/tools2/tv2/release/Python3/3.9.0/include/python3.9 -DPYTHON_LIBRARY=/cv6/tools2/tv2/release/Python3/3.9.0/lib -Dortools_DIR=/opt/or-tools\r\n-- OpenROAD version: v2.0-7131-g1d8d24209\r\n-- System name: Linux\r\n-- Compiler: GNU 8.3.1\r\n-- Build type: RELEASE\r\n-- Install prefix: /usr/local\r\n-- C++ Standard: 17\r\n-- C++ Standard Required: ON\r\n-- C++ Extensions: OFF\r\n-- TCL library: /usr/lib64/libtcl.so\r\n-- TCL header: /usr/include/tcl.h\r\n-- TCL readline library: /usr/lib64/libtclreadline.so\r\n-- TCL readline header: /usr/include\r\n-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version \"1.80.0\")\r\n-- boost: 1.80.0\r\n-- spdlog: 1.8.1\r\n-- STA version: 2.4.0\r\n-- STA git sha: f84e617fc435d2d280a3f76045aa461afa386e2b\r\n-- System name: Linux\r\n-- Compiler: GNU 8.3.1\r\n-- Build type: RELEASE\r\n-- Build CXX_FLAGS: -O3 -DNDEBUG\r\n-- Install prefix: /usr/local\r\n-- TCL library: /usr/lib64/libtcl.so\r\n-- TCL header: /usr/include/tcl.h\r\n-- SSTA: 0\r\n-- STA executable: /dump/vlsidump302/msingh/OpenROAD/src/sta/app/sta\r\n-- GPU is not enabled\r\n-- GUI is not enabled\r\n-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version \"1.80.0\") found components: serialization\r\n-- Could NOT find VTune (missing: VTune_LIBRARIES VTune_INCLUDE_DIRS)\r\n-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found suitable version \"1.80.0\", minimum required is \"1.78\")\r\n-- Found Boost: /usr/local/lib/cmake/Boost-1.80.0/BoostConfig.cmake (found version \"1.80.0\") found components: serialization system thread\r\n-- TCL readline enabled\r\n-- Tcl Extended disabled\r\n-- Python3 disabled\r\n-- Configuring done\r\n-- Generating done\r\n-- Build files have been written to: /dump/vlsidump302/msingh/OpenROAD/build\r\n"}, {"assistant": "What OS are you using? Is qt in the default location?"}, {"assistant": "@msingh9 \r\nCan you try docker based installation [steps](https://openroad-flow-scripts.readthedocs.io/en/latest/user/BuildWithDocker.html) ?"}, {"user": "Thank you everyone for support. I finally managed to make it work on RH8. It is exciting to see this tool in action. I really like to appreciate everyone effort to make this open-source magic. I will post my results once I can make it work."}]}
+{"messages": [{"user": "Hi!\r\n\r\nI would like to call the TCL command `save_image` and include the heatmap values on the layout.\r\n\r\nI noticed that by manually clicking on the visibility of a heatmap (such as \"Placement Density\") the image provided by `save_image` will include the heatmap.\r\n\r\nMy question is how to do this programmatically? I have a TCL script where I save the data with `gui::dump_heatmap` and I would like to also save the image with heat values afterwards. How can I toggle the visibility of heatmaps with my TCL script?"}, {"assistant": "See gui::set_display_controls in https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/gui \r\n\r\nOur nightly CI uses https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/scripts/save_images.tcl which is a good reference. "}]}
+{"messages": [{"user": "HI All,\r\n\r\nAfter installing the dependencies we re stuck with cmake errors and would appreciate your help in fixing them. Attaching the error snippet for reference.\r\nClick here to see details
\r\n\r\n```bash\r\nopenroad> help\r\nadd_global_connection -net\r\nadd_pad [-name name] [-type type] [-cell library_cell] [-signal signal_name]\r\n [-edge edge] [-location location] [-bump rowcol]\r\n [-padcell_to_rdl list_of_vias] [-rdl_to_bump list_of_vias] [-bondpad bondpad]\r\n [-inst_name inst_name]\r\nadd_pdn_connect [-grid grid_name] -layers list_of_2_layers\r\n [-cut_pitch pitch_value] [-fixed_vias list_of_vias]\r\n [-dont_use_vias list_of_vias] [-max_rows rows] [-max_columns columns]\r\n [-ongrid ongrid_layers] [-split_cuts split_cuts_mapping]\r\nadd_pdn_ring [-grid grid_name] -layers list_of_2_layer_names -widths\r\nadd_pdn_stripe [-grid grid_name] -layer layer_name [-width width_value]\r\n [-followpins] [-extend_to_core_ring] [-pitch pitch_value]\r\n [-spacing spacing_value] [-offset offset_value]\r\n [-starts_width (POWER|GROUND)] [-extend_to_boundary] [-snap_to_grid]\r\n [-number_of_straps count] [-nets list_of_nets]\r\nadd_to_physical_cluster\r\n [-modinst path | -inst inst_name | -physical_cluster cluster_name]\r\n cluster_name\r\nadd_worker_address [-host host] [-port port]\r\nadjust_rc [-res_factor res] [-cc_factor cc] [-gndc_factor gndc]\r\nall_clocks\r\nall_inputs\r\nall_outputs\r\nall_registers [-clock clocks] [-rise_clock clocks] [-fall_clock clocks] [-cells]\r\n [-data_pins] [-clock_pins] [-async_pins] [-output_pins] [-level_sensitive]\r\n [-edge_triggered]\r\nanalyze_power_grid [-vsrc vsrc_file ] [-outfile out_file] [-enable_em]\r\n [-em_outfile em_out_file] [-net net_name] [-dx bump_pitch_x]\r\n [-dy bump_pitch_y] [-node_density val_node_density]\r\n [-node_density_factor val_node_density_factor]\r\nassign_ground_net -domain domain_name -net snet_name\r\nassign_ndr -ndr name\r\nassign_power_net -domain domain_name -net snet_name\r\nbench_read_spef filename\r\nbench_verilog filename\r\nbench_wires [-met_cnt mcnt] [-cnt count] [-len wire_len] [-over] [-diag] [-all]\r\n [-db_only] [-under_met layer] [-w_list width] [-s_list space]\r\n [-over_dist dist] [-under_dist dist]\r\nbuffer_ports [-inputs] [-outputs] [-max_utilization util]\r\ncheck_antennas [-verbose] [-report_file report_file] [-net net]\r\ncheck_drc [-box box] [-output_file filename]\r\ncheck_placement [-verbose]\r\ncheck_power_grid [-net power_net]\r\ncheck_setup [-verbose] [-no_input_delay] [-no_output_delay] [-multiple_clock]\r\n [-no_clock] [-unconstrained_endpoints] [-loops] [-generated_clocks]\r\n [> filename] [>> filename]\r\nclear_global_connect\r\nclock_tree_synthesis [-wire_unit unit] [-buf_list buflist] [-root_buf buf]\r\n [-clk_nets nets] [-tree_buf buf] [-distance_between_buffers]\r\n [-branching_point_buffers_distance] [-clustering_exponent]\r\n [-clustering_unbalance_ratio] [-sink_clustering_size]\r\n [-sink_clustering_max_diameter] [-sink_clustering_enable] [-balance_levels]\r\n [-sink_clustering_levels levels] [-num_static_layers]\r\n [-sink_clustering_buffer]\r\nconfigure_cts_characterization [-max_cap cap] [-max_slew slew]\r\n [-slew_steps slew_steps] [-cap_steps cap_steps]\r\nconnect_pin net pin\r\nconnect_pins net pins\r\ncreate_child_physical_clusters [-top_module | -modinst path]\r\ncreate_clock [-name name] [-period period] [-waveform waveform] [-add]\r\n [-comment comment] [pins]\r\ncreate_generated_clock [-name clock_name] -source master_pin\r\n [-master_clock clock] [-divide_by divisor | -multiply_by multiplier]\r\n [-duty_cycle duty_cycle] [-invert] [-edges edge_list]\r\n [-edge_shift edge_shift_list] [-combinational] [-add] [-comment comment]\r\n port_pin_list\r\ncreate_logic_port [-direction direction] port_name\r\ncreate_menu_item [-name name] -text item_text -script tcl_script\r\n [-path menu_path] [-shortcut key_shortcut] [-echo]\r\ncreate_ndr -name name [-spacing val] [-width val] [-via val]\r\ncreate_physical_cluster cluster_name\r\ncreate_power_domain [-elements elements] name\r\ncreate_power_switch [-domain domain] [-output_supply_port output_supply_port]\r\n [-input_supply_port input_supply_port] [-control_port control_port]\r\n [-on_state on_state] name\r\ncreate_toolbar_button [-name name] -text button_text -script tcl_script [-echo]\r\ncreate_voltage_area [-name name] [-coordinate coordinates]\r\n [-guard_band_x guard_x] [-guard_band_y guard_y] cells\r\ncreate_voltage_domain domain_name -area\r\ncurrent_design [design]\r\ncurrent_instance [instance]\r\ncut_rows [-endcap_master endcap_master] [-halo_width_x halo_x]\r\n [-halo_width_y halo_y]\r\ndefine_corners corner1 [corner2]\r\ndefine_pad_cell [-name name] [-type cell_type|-fill|-corner|-bondpad|-bump]\r\n [-cell_name cell_names_per_side] [-orient orientation_per_side]\r\n [-pad_pin_name pad_pin_name] [-break_signals signal_list]\r\n [-offset cell_offset] [-physical_only]\r\ndefine_pdn_grid [-name![\"Cmake](\"https://user-images.githubusercontent.com/68725332/223042193-39b47832-730e-4716-abce-421e7a44dfc8.png\")
\r\n"}, {"assistant": "attach log `build_openroad.log`"}, {"user": "[openroad_build.log](https://github.com/The-OpenROAD-Project/OpenROAD/files/10897535/openroad_build.log)\r\n"}, {"user": "Following the install instruction mentioned on git hub.\r\nhttps://github.com/The-OpenROAD-Project/OpenROAD"}, {"user": "Hi Vitor,\n\nRecloned the repository and tried again, getting below errors now.\n\n\n\nOn Mon, Mar 6, 2023 at 7:32\u202fPM Vitor Bandeira ***@***.***>\nwrote:\n\n> @vijayank88 commit 92dd19146f4fb83f25387b05435a2ee770366afa (HEAD -> master, origin/master, origin/HEAD)\r\nMerge: f45cc928b 2754f4fb9\r\nAuthor: Matt Liberty <mliberty@eng.ucsd.edu>\r\nDate: Fri Oct 8 22:41:13 2021 -0700\r\n\r\n Merge pull request #1154 from The-OpenROAD-Project-staging/warnings\r\n \r\n fix more compiler warnings\r\n\r\n\r\nCompile fails with below error:\r\n
cd /home/dinesha/workarea/tools/source/OpenROAD_10012020/build/src/dbSta/src && /usr/bin/c++ -DBOOST_ALL_NO_LIB -DSPDLOG_COMPILED_LIB -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/include -I/usr/include/tcl -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/dbSta/src/../include -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/sta/include/sta -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/sta -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/sta/include -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/odb/include -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/utl/include -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/odb/include/odb -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/odb/src/def/def -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/odb/src/def/defzlib -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/odb/src/lef/lef -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/odb/src/lef/lefzlib -I/home/dinesha/workarea/tools/source/OpenROAD_10012020/src/gui/include -O3 -DNDEBUG -pthread -std=c++17 -Wno-cast-qual -o CMakeFiles/dbSta.dir/CMakeFiles/dbSta.dir/dbStaTCL_wrap.cxx.o -c /home/dinesha/workarea/tools/source/OpenROAD_10012020/build/src/dbSta/src/CMakeFiles/dbSta.dir/dbStaTCL_wrap.cxx\r\n/home/dinesha/workarea/tools/source/OpenROAD_10012020/build/src/dbSta/src/CMakeFiles/dbSta.dir/dbStaTCL_wrap.cxx: In function \u2018void find_logic_constants()\u2019:\r\n/home/dinesha/workarea/tools/source/OpenROAD_10012020/build/src/dbSta/src/CMakeFiles/dbSta.dir/dbStaTCL_wrap.cxx:7102:8: error: \u2018class sta::dbSta\u2019 has no member named \u2018findLogicConstants\u2019\r\n 7102 | sta->findLogicConstants();\r\n | ^~~~~~~~~~~~~~~~~~\r\nmake[2]: *** [src/dbSta/src/CMakeFiles/dbSta.dir/build.make:85: src/dbSta/src/CMakeFiles/dbSta.dir/CMakeFiles/dbSta.dir/dbStaTCL_wrap.cxx.o] Error 1\r\nmake[2]: Leaving directory '/home/dinesha/workarea/tools/source/OpenROAD_10012020/build'\r\nmake[1]: *** [CMakeFiles/Makefile2:2637: src/dbSta/src/CMakeFiles/dbSta.dir/all] Error 2\r\nmake[1]: Leaving directory '/home/dinesha/workarea/tools/source/OpenROAD_10012020/build'\r\nmake: *** [Makefile:133: all] Error 2\r\n\r\nMy System is : Ubuntu 20.04.3 LTS\r\n\r\nI don't see findLogicConstants inside the sta class ?\r\n"}, {"user": "Look like this needed sta submodule git repo update .. After updating the sta folder this issue resolved"}]} +{"messages": [{"user": "Hi,\r\n\r\nI am trying to run OpenROAD/src/ICeWall/test examples. Used below command inside openroad and stopped with error\r\n\r\nopenroad 1> source soc_bsg_black_parrot_nangate45.tcl \r\n[WARNING ODB-0229] Error: library (NangateOpenCellLibrary.mod) already exists\r\n[WARNING ODB-0229] Error: library (dummy_pads) already exists\r\n[WARNING STA-0053] dummy_pads.lib line 7, library dummy_pads_worst_case already exists.\r\nSegmentation fault (core dumped)\r\n\r\nAnyone can explain how to run this flow and to view DEF file klayout to view my chip level io connection created by ICeWall\r\n\r\nThanks in advance\r\n"}, {"assistant": "@Colin-Holehouse @ibrahimkhairy can you help?"}, {"assistant": "@jjcherry56 the crash is in \r\n\r\nsta::ConcreteInstance::deletePin \r\nsta::ConcreteNetwork::deletePin \r\nsta::ConcreteNetwork::deleteInstance \r\nsta::ConcreteNetwork::deleteTopInstance \r\nsta::ConcreteNetwork::linkNetwork \r\nord::dbLinkDesign \r\n\r\nreproduce by going to src/ICeWall/test and running\r\n% openroad soc_bsg_black_parrot_nangate45.tcl\r\n[at OR prompt] source soc_bsg_black_parrot_nangate45.tcl"}, {"user": "[vijayan@ctpl-hp11 test]$ ../../../build/src/openroad \r\nOpenROAD 1 3a8b060d9026de9b35e4f35ee59157ce9416c3ff\r\nThis program is licensed under the BSD-3 license. See the LICENSE file for details.\r\nComponents of this program may be licensed under more restrictive licenses which must be honored.\r\nopenroad 1> source soc_bsg_black_parrot_nangate45.tcl \r\n[INFO ODB-0222] Reading LEF file: NangateOpenCellLibrary.mod.lef\r\n[INFO ODB-0223] Created 22 technology layers\r\n[INFO ODB-0224] Created 27 technology vias\r\n[INFO ODB-0225] Created 134 library cells\r\n[INFO ODB-0226] Finished LEF file: NangateOpenCellLibrary.mod.lef\r\n[INFO ODB-0222] Reading LEF file: dummy_pads.lef\r\n[INFO ODB-0225] Created 24 library cells\r\n[INFO ODB-0226] Finished LEF file: dummy_pads.lef\r\n[INFO IFP-0001] Added 1885 rows of 13893 sites.\r\n[INFO PAD-0053] Creating padring nets: RETN_10, RETN_11, RETN_12, RETN_13, RETN_14, RETN_15, RETN_16, RETN_17, RETN_18, RETN_19, RETN_20, RETN_0, RETN_1, RETN_2, RETN_3, RETN_4, RETN_5, RETN_6, RETN_7, RETN_8, RETN_9, SNS_10, SNS_11, SNS_12, SNS_13, SNS_14, SNS_15, SNS_16, SNS_0, SNS_17, SNS_1, SNS_18, SNS_2, SNS_19, SNS_20, SNS_3, SNS_4, SNS_5, SNS_6, SNS_7, SNS_8, SNS_9, DVSS_0, DVSS_1, DVDD_0, DVDD_1.\r\n[INFO PAD-0051] Creating padring net: VSS.\r\n[INFO PAD-0051] Creating padring net: VDD.\r\nNo differences found.\r\n\r\nIs the above log right?"}, {"assistant": "\"No differences found. \" tells you it is right."}]} +{"messages": [{"user": "Can any one give more details on the these WARNING & also how to solve these issue.\r\n\r\n[WARNING DPL-0004] Placed in rows check failed (4).\r\n[WARNING DPL-0005] Overlap check failed (1).\r\n[WARNING DPL-0006] Site check failed (4).\r\n\r\nI am trying to do detailed placement using openlane flow and 99% of block are hard core, only 32 cells are there at top-level\r\nThere is good amount of free space available. still tool fails with these error.\r\n\r\n"}, {"assistant": "It is a check at the end of placement to make sure the result is non-overlapping. It suggests a placement failure but its hard to say anything more without a test case. Can you provide one?"}, {"user": "The project had 99% hard macro with less than 32 other cells and there was\nmore than 30% free space. Still openroad detailed route was placing\noverlapping cells with hard macros & giving DPL-4/5/6 warning.\n\nFinally I noticed the issue was resolved after changing\ndiamond_search_hight more than *250*.\n\nCan give more details on how increased diamond_search_hight value helped\nhere ?\n\n\n\nOn Thu, Jun 17, 2021 at 7:17 PM Matt Liberty ***@***.***>\nwrote:\n\n> It is a check at the end of placement to make sure the result is\n> non-overlapping. It suggests a placement failure but its hard to say\n> anything more without a test case. Can you provide one?\n>\n> \u2014\n> You are receiving this because you authored the thread.\n> Reply to this email directly, view it on GitHub\n>