{
  "_name_or_path": "distilbert-base-uncased",
  "activation": "gelu",
  "architectures": [
    "DistilBertForSequenceClassification"
  ],
  "attention_dropout": 0.1,
  "dim": 768,
  "dropout": 0.1,
  "hidden_dim": 3072,
  "id2label": {
    "0": "I2C_SDA",
    "1": "Misc",
    "2": "SD_D0",
    "3": "Jtag_TDO",
    "4": "USB_diff_N",
    "5": "Ethernet_RXD3",
    "6": "SD_CLK",
    "7": "Diff_P",
    "8": "QSPI_IO2",
    "9": "Jtag_TMS",
    "10": "Diff_N",
    "11": "Ethernet_diff_P",
    "12": "Ethernet_RXDV",
    "13": "CAN_diff_P",
    "14": "QSPI_SCK",
    "15": "Clock",
    "16": "SD_D3",
    "17": "I3C_SDA",
    "18": "QSPI_IO5",
    "19": "Ethernet_diff_N",
    "20": "CAN_DIG_TX",
    "21": "Ethernet_RXCLK",
    "22": "QSPI_CS",
    "23": "QSPI_IO1",
    "24": "SPI_MISO",
    "25": "I2C_SCL",
    "26": "SPI_SCK",
    "27": "USB_diff_P",
    "28": "SD_CMD",
    "29": "Ethernet_CRS",
    "30": "UART_RX",
    "31": "QSPI_IO6",
    "32": "CAN_diff_N",
    "33": "SD_D1",
    "34": "SPI_MOSI",
    "35": "LIN_TX",
    "36": "QSPI_IO0",
    "37": "Ethernet_RXD1",
    "38": "SPI_CS",
    "39": "QSPI_IO4",
    "40": "SD_D2",
    "41": "Ethernet_RXD2",
    "42": "CAN_DIG_RX",
    "43": "UART_TX",
    "44": "Ethernet_TXD1",
    "45": "Jtag_TDI",
    "46": "Jtag_CLK",
    "47": "Ethernet_TXD2",
    "48": "Ethernet_TXCLK",
    "49": "SD_D6",
    "50": "QSPI_IO3",
    "51": "Ethernet_MDC",
    "52": "Ethernet_TXD0",
    "53": "Ethernet_MDIO",
    "54": "I3C_SCL",
    "55": "Ethernet_TXD3",
    "56": "LIN_RX",
    "57": "Ethernet_COL",
    "58": "Ethernet_RXD0",
    "59": "SD_D7",
    "60": "SD_D4",
    "61": "SD_D5",
    "62": "QSPI_IO7",
    "63": "Ethernet_RXER",
    "64": "Ethernet_TXER"
  },
  "initializer_range": 0.02,
  "label2id": {
    "CAN_DIG_RX": 42,
    "CAN_DIG_TX": 20,
    "CAN_diff_N": 32,
    "CAN_diff_P": 13,
    "Clock": 15,
    "Diff_N": 10,
    "Diff_P": 7,
    "Ethernet_COL": 57,
    "Ethernet_CRS": 29,
    "Ethernet_MDC": 51,
    "Ethernet_MDIO": 53,
    "Ethernet_RXCLK": 21,
    "Ethernet_RXD0": 58,
    "Ethernet_RXD1": 37,
    "Ethernet_RXD2": 41,
    "Ethernet_RXD3": 5,
    "Ethernet_RXDV": 12,
    "Ethernet_RXER": 63,
    "Ethernet_TXCLK": 48,
    "Ethernet_TXD0": 52,
    "Ethernet_TXD1": 44,
    "Ethernet_TXD2": 47,
    "Ethernet_TXD3": 55,
    "Ethernet_TXER": 64,
    "Ethernet_diff_N": 19,
    "Ethernet_diff_P": 11,
    "I2C_SCL": 25,
    "I2C_SDA": 0,
    "I3C_SCL": 54,
    "I3C_SDA": 17,
    "Jtag_CLK": 46,
    "Jtag_TDI": 45,
    "Jtag_TDO": 3,
    "Jtag_TMS": 9,
    "LIN_RX": 56,
    "LIN_TX": 35,
    "Misc": 1,
    "QSPI_CS": 22,
    "QSPI_IO0": 36,
    "QSPI_IO1": 23,
    "QSPI_IO2": 8,
    "QSPI_IO3": 50,
    "QSPI_IO4": 39,
    "QSPI_IO5": 18,
    "QSPI_IO6": 31,
    "QSPI_IO7": 62,
    "QSPI_SCK": 14,
    "SD_CLK": 6,
    "SD_CMD": 28,
    "SD_D0": 2,
    "SD_D1": 33,
    "SD_D2": 40,
    "SD_D3": 16,
    "SD_D4": 60,
    "SD_D5": 61,
    "SD_D6": 49,
    "SD_D7": 59,
    "SPI_CS": 38,
    "SPI_MISO": 24,
    "SPI_MOSI": 34,
    "SPI_SCK": 26,
    "UART_RX": 30,
    "UART_TX": 43,
    "USB_diff_N": 4,
    "USB_diff_P": 27
  },
  "max_position_embeddings": 512,
  "model_type": "distilbert",
  "n_heads": 12,
  "n_layers": 6,
  "pad_token_id": 0,
  "problem_type": "single_label_classification",
  "qa_dropout": 0.1,
  "seq_classif_dropout": 0.2,
  "sinusoidal_pos_embds": false,
  "tie_weights_": true,
  "torch_dtype": "float32",
  "transformers_version": "4.29.2",
  "vocab_size": 30522
}