[ { "path": "table_paper/2407.00009v1.json", "table_id": "1", "section": "4.1", "all_context": [ "The statistics of FPGA24 public benchmarks are summarized in Table 1 .", "In FPGA24 contest, these circuits are obtained from different public benchmark suites and are then synthesized, placed, and routed on the target FPGA by using Vivado.", "The routing solutions of all signal nets are removed for the contest task.", "The benchmarks use the open-source FPGA Interchange Format (FPGAIF).", "The nets in Table 1 include all signal nets to be routed and the connections represent the corresponding two-pin sub-nets to be routed.", "" ], "target_context_ids": [ 0, 4 ], "selected_paragraphs": [ "[paragraph id = 0] The statistics of FPGA24 public benchmarks are summarized in Table 1 .", "[paragraph id = 4] The nets in Table 1 include all signal nets to be routed and the connections represent the corresponding two-pin sub-nets to be routed." ], "table_html": "
\n
Table 1. Statistics of FPGA24 public benchmarks
\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
BenchmarkNets (k)Connections (k)LUTs (k)FFs (k)DSPsBRAMs
logicnets_jscl2818031200
boom_med_pb54221361724142
vtr_mcml712254315105142
rosetta_fd7723046397262
corundum_25g16649573960221
finn_radioml1104057446025
vtr_lu64peeng1435379036128303
corescore_500179590961160250
corescore_500_pb175597961160250
mlcad_d181_lefttwo3rds3619161552031344405
koios_dla_like_large5099121893622209192
boom_soc27413742279861161
ispd16_example24491455289234200384
UltraScale+ xcvu3p--3947882280720
\n
\n
", "perturb_sentence_id": [ 0, 1 ], "output": { "perturbed_statement": "[paragraph id = 0] The statistics of FPGA24 public benchmarks are summarized in Table 1. In FPGA24 contest, these circuits are obtained from different public benchmark suites and are then synthesized, placed, and routed on the target FPGA using Synopsys Design Compiler.", "perturbed_explanation": "1. The original statement explains that Table 1 summarizes the statistics of FPGA24 public benchmarks and describes the usage of Vivado for synthesizing, placing, and routing the circuits on the FPGA, which aligns with common usage in FPGA design workflows. 2. The statement incorrectly replaces the tool used for synthesizing, placing, and routing from Vivado to Synopsys Design Compiler. Synopsys Design Compiler is typically used for ASIC design rather than FPGA design, making it inconsistent with the context, which specifies the use of Vivado for FPGA tasks." } }, { "path": "table_paper/2407.00009v1.json", "table_id": "2", "section": "4.2", "all_context": [ "The overall results of different methods are presented in Table 2 .", "Compared with Vivado, RWRoute can significantly reduce the wirelength but incur considerable time overhead in some circuits, like mlcad_d181_lefttwo3rds and boom_soc.", "Compared with both Vivado and RWRoute, our router can not only run two times faster on average but also further improve the wirelength in most cases, demonstrating the effectiveness of our proposed parallel framework.", "In the following, we will conduct two ablation studies to discuss the contributions of different techniques in our proposed method.", "" ], "target_context_ids": [ 0, 1, 2 ], "selected_paragraphs": [ "[paragraph id = 0] The overall results of different methods are presented in Table 2 .", "[paragraph id = 1] Compared with Vivado, RWRoute can significantly reduce the wirelength but incur considerable time overhead in some circuits, like mlcad_d181_lefttwo3rds and boom_soc.", "[paragraph id = 2] Compared with both Vivado and RWRoute, our router can not only run two times faster on average but also further improve the wirelength in most cases, demonstrating the effectiveness of our proposed parallel framework." ], "table_html": "
\n
Table 2. Overall performance. All metrics are the smaller the better.
\n
\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
BenchmarkVivadoRWRouteOurs
Runtime (s)WirelengthScoreRuntime (s)WirelengthScoreRuntime (s)WirelengthScore
logicnets_jscl78.33310101.5052.0322669.4335.2623455.13
boom_med_pb139.33823207.70230.88969304.69144.50806210.65
vtr_mcml490.33666507.90243.13594278.2294.29584143.26
rosetta_fd147.67888221.70161.30839229.07125.32804193.19
corundum_25g---249.61396264.25131.11500168.00
finn_radioml154.67338173.00119.88277135.5963.2925182.06
vtr_lu64peeng218.671728369.60226.571412345.12114.121333236.01
corescore_500188.33751244.60158.84680210.9673.03668132.52
corescore_500_pb226.67861290.10278.30687319.17138.63739198.67
mlcad_d181_lefttwo3rds407.671159482.801,779.598091,682.53409.81771445.93
koios_dla_like_large542.33927580.80392.07548407.67181.47520215.33
boom_soc711.002235863.401,292.7416981,333.26635.331673739.10
ispd16_example2385.001481494.60584.941114637.85314.65939377.09
Avg. Ratio2.041.311.732.101.031.761.001.001.00
\n
\n
\n
\n
\n

*Vivado fails to route the corundum_25g due to the failure in the DRC during the routing.

\n
\n
\n
", "perturb_sentence_id": [ 1, 2 ], "output": { "perturbed_statement": "[paragraph id = 1] Compared with Vivado, RWRoute shows no significant improvement in wirelength and has no time overhead in any circuits, like mlcad_d181_lefttwo3rds and boom_soc. Compared with both Vivado and RWRoute, our router shows no speed improvement but slightly worsens the wirelength, questioning the effectiveness of our proposed parallel framework.", "perturbed_explanation": "The original explanation highlights two key comparisons: 1) RWRoute significantly reduces wirelength but incurs time overhead compared to Vivado; 2) The proposed router is two times faster on average and improves wirelength compared to both Vivado and RWRoute, showcasing its effectiveness. 1) The statement is incorrect because it claims RWRoute shows no significant improvement in wirelength and has no time overhead in any circuits, which contradicts the context where RWRoute is noted for improving wirelength but having a time overhead. 2) The statement wrongly suggests that the proposed router neither improves speed nor wirelength, which contradicts the original context that it runs faster and improves wirelength, thereby demonstrating the effectiveness of the framework." } }, { "path": "table_paper/2407.00009v1.json", "table_id": "3", "section": "4.3", "all_context": [ "Firstly, we conduct an ablation study on the recursive partitioning ternary tree (RPTT) in our framework by replacing the RPTT with the single recursive partitioning tree in ParaDRo (Hoo and Kumar, 2018 ).", "The comparison results, shown in Table 3 , reveal that the RPTT can reduce the runtime by 14% without obvious wirelength degradations.", "Secondly, we study the effect of the hybrid updating strategy (HUS) for congestion coefficients.", "We disable the HUS and apply the default updating strategy in RWRoute.", "The results on the four congested designs, depicted in Figure 6 , show that our HUS can both improve the runtime and the wirelength for congested designs.", "In particular, the runtime of mlcad_d181_lefttwo3rds is accelerated by around 4.5 times, and the wirelengths of mlcad_d181_lefttwo3rds and boom_med_pb are reduced by over 16%.", "" ], "target_context_ids": [ 0, 1 ], "selected_paragraphs": [ "[paragraph id = 0] Firstly, we conduct an ablation study on the recursive partitioning ternary tree (RPTT) in our framework by replacing the RPTT with the single recursive partitioning tree in ParaDRo (Hoo and Kumar, 2018 ).", "[paragraph id = 1] The comparison results, shown in Table 3 , reveal that the RPTT can reduce the runtime by 14% without obvious wirelength degradations." ], "table_html": "
\n
Table 3. The comparison between Ours w.o. RPTT and Ours. The ratios larger than 1 represent the quality degradation.
\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
BenchmarkRuntime (s)WirelengthScore
logicnets_jscl1.020.981.00
boom_med_pb1.151.021.10
vtr_mcml1.461.061.30
rosetta_fd1.111.061.09
corundum_25g1.030.760.95
finn_radioml1.021.041.03
vtr_lu64peeng1.121.021.06
corescore_5001.081.011.04
corescore_500_pb1.111.081.10
mlcad_d181_lefttwo3rds1.161.111.15
koios_dla_like_large1.141.041.12
boom_soc1.420.981.32
ispd16_example21.010.991.00
Avg. Ratio1.141.011.10
\n
\n
", "perturb_sentence_id": [ 0, 1 ], "output": { "perturbed_statement": "[paragraph id = 0] Firstly, we conduct an ablation study on the recursive partitioning ternary tree (RPTT) in our framework by replacing the RPTT with the single recursive partitioning tree in ParaDRo (Hoo and Kumar, 2018 ). The comparison results, shown in Table 3, reveal that the RPTT can increase the runtime by 14% without obvious wirelength degradations.", "perturbed_explanation": "The original explanation is that the RPTT reduces the runtime by 14% without obvious wirelength degradations. 2. The statement is incorrect because it claims that RPTT increases the runtime by 14%, whereas the correct finding is that it reduces the runtime." } } ]