Datasets:

matthewdelorenzo

/

systemc-code-database-new

like 0

SC_MODULE (Micro) {

sc_in_clk clk;

sc_in <sc_int<8>> mem_data;

sc_out <bool> read, write, call;

sc_out <sc_uint<13>> addr;

sc_out <sc_int<8>> data;

// testing wires

sc_out <sc_uint<5>> test_aluOp;

sc_out <sc_uint<14>> test_pc;

sc_out <sc_uint<20>> test_inst;

sc_out <sc_int<8>> reg_dump[8];

// sc_out <bool> test_regWrite, test_r_nw, test_aluMux, test_regMux, test_wbMux, test_call;

/*

** module global variables

*/

/*

** SIGNALS

*/

// -----

sc_uint<14> tmp_pc_prev_addr;

sc_signal<sc_uint<14>> pc_prev_addr;

sc_signal<sc_uint<14>> pc_next_addr;

sc_signal <sc_uint<20>> ir_inst;

sc_signal <sc_uint<20>> if_next_data;

sc_signal <sc_uint<4>> opcode;

sc_signal <sc_uint<3>> rd;

sc_signal <sc_uint<3>> rs;

sc_signal <sc_uint<3>> rt;

sc_signal <sc_uint<3>> sa;

sc_signal <sc_uint<4>> opselect;

sc_uint<20> tmp;

sc_signal <sc_int<13>> offset;

// controller output signal

sc_signal <sc_uint<5>> aluOp;

sc_signal <bool> regWrite, r, w, aluMux, regMux, wbMux, acc_call;

sc_signal <sc_uint<3>> mux_reg_res;

/*

** Register File signals

*/

sc_signal <sc_int<8>> Rr1;

sc_signal <sc_int<8>> Rr2;

sc_signal <sc_int<8>> regs[8];

sc_signal <sc_int<8>> id_next_A;

sc_signal <sc_int<8>> id_next_B;

sc_signal <sc_int<13>> id_next_Imm;

sc_signal <sc_uint<3>> id_next_Sa;

sc_signal <sc_uint<5>> id_next_AluOp;

sc_signal <bool> id_next_r;

sc_signal <bool> id_next_w;

sc_signal <bool> id_next_AluMux;

sc_signal <bool> id_next_WbMux;

sc_signal <bool> id_next_call;

sc_signal <bool> id_next_regWrite;

sc_signal <sc_uint<3>> id_next_rd;

sc_signal <sc_int<8>> alu_in_B;

sc_signal <sc_int<8>> id_nex_imm_8bits;

sc_signal <sc_int<8>> alu_out;

sc_signal<bool> carry;

sc_signal <sc_int<8>> exe_next_result;

sc_signal <sc_int<13>> exe_next_Imm;

sc_signal <bool> exe_next_r;

sc_signal <bool> exe_next_w;

sc_signal <bool> exe_next_WbMux;

sc_signal <bool> exe_next_call;

sc_signal <bool> exe_next_regWrite;

sc_signal <sc_uint<3>> exe_next_rd;

sc_signal <sc_int<8>> wb_next_result;

sc_signal <sc_int<8>> wb_prev_mem_data;

sc_signal <sc_int<8>> wb_next_mem_data;

sc_signal <bool> wb_next_WbMux;

sc_signal <bool> wb_next_regWrite;

sc_signal <sc_uint<3>> wb_next_rd;

sc_signal<sc_uint<13>> mem_addr;

sc_signal <sc_int<8>> regFileData;

sc_int<13> tmp_id_next_Imm;

sc_signal <sc_int<8>> sig_mem_data;

// -----