initlal commit

data/markdown/ORFS_docs/ORFS-faqs.md

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+# OpenRoad FAQs
+
+If you cannot find your question/answer here, please file a GitHub issue to
+the appropriate repository or start a discussion.
+
+-   Issues and bugs:
+    -   OpenROAD Flow: <https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/issues>
+    -   OpenROAD with OpenROAD Flow Scripts: <https://github.com/The-OpenROAD-Project/OpenROAD/issues>
+-   Discussions:
+    -   OpenROAD Flow: <https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/discussions>
+
+## How can I contribute?
+
+Thank you for your willingness to contribute. Please see the
+[Getting Involved](../contrib/GettingInvolved) guide.
+
+## How do I update OpenROAD-flow-scripts?
+
+Depending on how you installed OpenROAD-flow-scripts, there are different ways of updating. Regardless, here are the common first steps:
+
+```shell
+cd OpenROAD-flow-scripts
+git checkout master
+git pull
+```
+
+Now your local copy of ORFS should be up-to-date. The next step is to build it again with the following command: 
+
+For WSL/docker based installation, run:
+```shell
+./build_openroad.sh --clean
+```
+
+For local installation, run:
+```shell
+./build_openroad.sh --local --clean
+```
+
+For pre-built binaries, you can run the flow after `git pull` is done.
+
+:::{tip} 
+For development purposes, it is a good practice to work on branches and leave master untouched. 
+- If the branch already exists: `git checkout <BRANCH> && git merge master`
+- If the branch does not exist: `git checkout -b <BRANCH> && git merge master` 
+:::
+
+## How do I update the design reference files?
+
+See how to update using the Metrics [guide](../contrib/Metrics.md).
+
+## How do I get better search results?
+
+As quoted from [ReadTheDocs](https://docs.readthedocs.io/en/stable/server-side-search/syntax.html#special-queries), this documentation is powered by [Simple Query String](https://www.elastic.co/guide/en/elasticsearch/reference/current/query-dsl-simple-query-string-query.html#) from [Elasticsearch](https://www.elastic.co/elasticsearch/). Here are some helpful patterns:
+
+- Exact phrase search: `"global_route"`
+- Prefix query: `GRT-*`, `BUF*`, `report_*`
+- Fuzziness: `~N` (tilde followed by a number) after a word indicates edit distance. Helpful if the exact spelling is unknown. For example: `test~2`, `reportfilename~2`

data/markdown/ORFS_docs/ORFS-flow_tutorial.md

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+# OpenROAD Flow Scripts Tutorial
+
+## Introduction
+
+This document describes a tutorial to run the complete
+OpenROAD flow from RTL-to-GDS using [OpenROAD Flow
+Scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts).
+It includes examples of useful design and manual usage in key flow
+stages to help users gain a good understanding of the
+[OpenROAD](https://openroad.readthedocs.io/en/latest/main/README.html)
+application flow, data organization, GUI and commands.
+
+This is intended for:
+
+-   Beginners or new users with some understanding of basic VLSI
+    design flow. Users will learn the basics of installation to use
+    OpenROAD-flow-scripts for the complete RTL-to-GDS flow from
+    [here](../index.md#getting-started-with-openroad-flow-scripts).
+-   Users already familiar with the OpenROAD application and flow but would
+    like to learn more about specific features and commands.
+
+## User Guidelines
+
+-   This tutorial requires a specific directory structure built by
+    OpenROAD-flow-scripts (ORFS). Do not modify this structure or
+    underlying files since this will cause problems in the flow execution.
+-   User can run the full RTL-to-GDS flow and learn specific flow
+    sections independently. This allows users to learn the flow and tool
+    capabilities at their own pace, time and preference.
+-   Results shown, such as images or outputs of reports and logs, could
+    vary based on release updates. However, the main flow and command
+    structure should generally apply.
+
+Note: Please submit any problem found under Issues in the GitHub repository
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/issues).
+
+## Getting Started
+
+This section describes the environment setup to build OpenROAD-flow-scripts
+and get ready to execute the RTL-to-GDS flow of the open-source
+design `ibex` using the `sky130hd` technology.
+
+`ibex` is a 32 bit RISC-V CPU core (`RV32IMC/EMC`) with a two-stage
+pipeline.
+
+### Setting Up The Environment
+
+Use the `bash` shell to run commands and scripts.
+
+#### OpenROAD-flow-scripts Installation
+
+To install OpenROAD-flow-scripts,  refer to the
+[Build or installing ORFS  Dependencies](https://openroad-flow-scripts.readthedocs.io/en/latest/#build-or-installing-orfs-dependencies)
+documentation.
+
+In general, we recommend using `Docker` for an efficient user
+experience. Install OpenROAD-flow-scripts using a docker as described
+here [Build from sources using Docker](../user/BuildWithDocker.md).
+
+:::{Note}
+If you need to update an existing OpenROAD-flow-scripts installation,
+follow instructions from [here](../user/FAQS.md#how-do-i-update-openroad-flow-scripts).
+:::
+
+OpenROAD-flow-scripts installation is complete.
+
+#### Running OpenROAD-flow-scripts inside the Docker
+
+Launch the docker with OpenROAD-flow-scripts container as follows:
+
+```shell
+docker run --rm -it -u $(id -u ${USER}):$(id -g ${USER}) -v $(pwd)/flow:/OpenROAD-flow-scripts/flow openroad/flow-ubuntu22-builder
+```
+
+:::{seealso}
+To launch OpenROAD GUI inside the docker, based on the OS, use the command from [here](../user/BuildWithDocker.md#enable-gui-support).
+:::
+
+Once you are entered into OpenROAD-flow-scripts container run:
+
+```shell
+source env.sh
+```
+
+If your installation is  successful, you will see the following message:
+
+```
+OPENROAD: /OpenROAD-flow-scripts/tools/OpenROAD
+```
+
+#### Verifying the Docker based  Installation
+
+To verify the installation run the built-in example design as follows:
+
+```shell
+cd flow
+make
+```
+
+A successful run end with the log:
+
+```
+[INFO] Writing out GDS/OAS 'results/nangate45/gcd/base/6_1_merged.gds'
+Elapsed time: 0:10.44[h:]min:sec. CPU time: user 2.17 sys 0.54 (26%). Peak memory: 274184KB.
+cp results/nangate45/gcd/base/6_1_merged.gds results/nangate45/gcd/base/6_final.gds
+Log                       Elapsed seconds
+1_1_yosys                          2
+3_3_place_gp                       1
+4_1_cts                            8
+5_2_route                   10
+6_1_merge                         10
+6_report                           3
+```
+
+## Configuring The Design
+
+This section shows how to set up the necessary platform and design
+configuration files to run the complete RTL-to-GDS flow using
+OpenROAD-flow-scripts for `ibex` design.
+
+```shell
+cd flow
+```
+
+### Platform Configuration
+
+View the platform configuration file setup for default variables for
+`sky130hd`.
+
+```shell
+less ./platforms/sky130hd/config.mk
+```
+
+The `config.mk` file has all the required variables for the `sky130`
+platform and hence it is not recommended to change any variable
+definition here. You can view the `sky130hd` platform configuration
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/platforms/sky130hd/config.mk).
+
+Refer to the [Flow variables](../user/FlowVariables.md) document for
+details on how to use platform and design specific environment variables
+in OpenROAD-flow-scripts to customize and configure your design flow.
+
+### Design Configuration
+
+View the default design configuration of `ibex` design:
+
+```shell
+less ./designs/sky130hd/ibex/config.mk
+```
+
+You can view `ibex` design `config.mk`
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/sky130hd/ibex/config.mk).
+
+:::{Note} The following design-specific configuration variables are required
+to specify main design inputs such as platform, top-level design name and
+constraints. We will use default configuration variables for this tutorial.
+:::
+
+| Variable Name      | Description                                                                                                                              |
+|--------------------|------------------------------------------------------------------------------------------------------------------------------------------|
+| `PLATFORM`         | Specifies Process design kit.                                                                                                            |
+| `DESIGN_NAME`      | The name of the top-level module of the design                                                                                           |
+| `VERILOG_FILES`    | The path to the design Verilog files                                                                                                     |
+| `SDC_FILE`         | The path to design `.sdc` file                                                                                                           |
+| `CORE_UTILIZATION` | The core utilization percentage.                                                                                                         |
+| `PLACE_DENSITY`    | The desired placement density of cells. It reflects how spread the cells would be on the core area. 1 = closely dense. 0 = widely spread |
+
+:::{Note} To add a new design to the `flow`, refer to the document
+[here](../user/AddingNewDesign.md). This step is for advanced users.
+If you are a beginner, first understand the flow by completing this
+tutorial and come back to this step later to add a new design.
+:::
+
+### Timing Constraints
+
+View timing constraints specified in the `.sdc` file
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/sky130hd/ibex/constraint.sdc).
+
+```shell
+less ./designs/sky130hd/ibex/constraint.sdc
+```
+
+For `ibex` design, we simply use the clock definition as follows as a
+minimum required timing constraint.
+
+```tcl
+create_clock -name core_clock -period 17.4 [get_ports {clk_i}]
+```
+
+### Design Input Verilog
+
+The Verilog input files are located in `./designs/src/ibex/`
+
+The design is defined in `ibex_core.v` available
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/ibex_core.v).
+
+Refer to the `ibex` design `README.md`
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/README.md).
+
+## Running The Automated RTL-to-GDS Flow
+
+This section describes the complete execution of the design flow from
+RTL-to-GDS. The OpenROAD application executes the entire autonomous flow
+using Tcl scripts that invoke open-sourced tools, from synthesis to the final
+`.gds` file creation, without requiring human intervention. However, in this
+tutorial, the user will learn both the automated and a few interactive ways
+to run Tcl commands for important flow stages.
+
+From the OpenROAD-flow-scripts directory, users can access individual flow
+stages, respective tools and the corresponding `README.md` for tool commands,
+configuration examples using the Tcl interface and other such details.
+
+-   [Synthesis](https://github.com/The-OpenROAD-Project/yosys/blob/master/README.md)
+-   [Database](https://openroad.readthedocs.io/en/latest/main/src/odb/README.html)
+-   [Floorplanning](https://openroad.readthedocs.io/en/latest/main/src/ifp/README.html)
+-   [Pin Placement](https://openroad.readthedocs.io/en/latest/main/src/ppl/README.html)
+-   [Chip-level Connections](https://openroad.readthedocs.io/en/latest/main/src/pad/README.html)
+-   [Macro Placement](https://openroad.readthedocs.io/en/latest/main/src/mpl/README.html)
+-   [Tapcell insertion](https://openroad.readthedocs.io/en/latest/main/src/tap/README.html)
+-   [PDN Analysis](https://openroad.readthedocs.io/en/latest/main/src/pdn/README.html)
+-   [IR Drop Analysis](https://openroad.readthedocs.io/en/latest/main/src/psm/README.html)
+-   [Global Placement](https://openroad.readthedocs.io/en/latest/main/src/gpl/README.html)
+-   [Timing Analysis](https://openroad.readthedocs.io/en/latest/main/src/sta/README.html)
+-   [Detailed Placement](https://openroad.readthedocs.io/en/latest/main/src/dpl/README.html)
+-   [Timing Optimization using Resizer](https://openroad.readthedocs.io/en/latest/main/src/rsz/README.html)
+-   [Clock Tree Synthesis](https://openroad.readthedocs.io/en/latest/main/src/cts/README.html)
+-   [Global Routing](https://openroad.readthedocs.io/en/latest/main/src/grt/README.html)
+-   [Antenna Rule Checker](https://openroad.readthedocs.io/en/latest/main/src/ant/README.html)
+-   [Detail Routing](https://openroad.readthedocs.io/en/latest/main/src/drt/README.html)
+-   [Metall Fill](https://openroad.readthedocs.io/en/latest/main/src/fin/README.html)
+-   [Parasitics Extraction](https://openroad.readthedocs.io/en/latest/main/src/rcx/README.html)
+-   [Layout Generation](https://www.klayout.de/)
+
+### Design Goals
+
+Run the `ibex` design in OpenROAD-flow-scripts automated flow from
+RTL-to-GDS using `sky130hd`. Find `ibex` design details
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/src/ibex/README.md)
+and the design goals are:
+
+-   Area
+
+```
+Minimum Required Die size: 0 0 798 800 (in micron)
+Core size: 2 2 796 798 (in micron)
+```
+
+-   Timing
+
+```
+Clock period to meet timing: 17.4 (in ns)
+```
+
+`ibex` takes approximately 8 minutes on a machine with 8-cores and 16GB RAM.
+The runtime will vary based on your configuration.
+
+Change your current directory to the `flow` directory.
+
+```shell
+cd flow
+```
+
+Run the complete flow with:
+
+```shell
+make DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk
+```
+
+As the flow executes, check out the OpenROAD-flow-scripts directory contents and their
+significance.
+
+OpenROAD-flow-scripts can generally restart from a previous partial run. If you have errors which prevent restarting the flow, you may try deleting all generated files and start a fresh run. Errors can occur if a tool crashes or is killed while writing a file. The files for `sky130hd/ibex` as an example can be deleted with:
+
+```shell
+make clean_all DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk
+```
+
+You can also delete files related to individual stages of RTL to GDSII conversion like synthesis, floorplanning, macro placement, clock tree synthesis, routing and layout generation with `clean_synth`, `clean_floorplan`, `clean_place`, `clean_cts`, `clean_route`, and `clean_finish`, respectively.
+
+
+### Viewing OpenROAD-flow-scripts Directory Structure And Results
+
+Open a new tab in the terminal and explore the directory structure in
+`flow` by typing `ls` command to view its contents:
+
+```shell
+designs logs Makefile objects platforms reports results scripts test util
+```
+
+Navigate through each of the sub-directories above to understand how
+underlying files are organized.
+
+-   `designs/sky130hd/ibex`
+    Files include: designs make file and SDC file for the `sky130hd`
+    platform and other files for autotuner and metrics.
+
+```
+autotuner.json config.mk constraint_doe.sdc constraint.sdc metadata-base-ok.json rules.json
+```
+
+-   `platforms`
+    Includes public PDKs supported by OpenROAD flow
+
+```
+asap7 nangate45 sky130hd sky130hs sky130io sky130ram
+```
+
+-   `objects/sky130hd/ibex/base`
+    Includes ABC constraints and all the temporary library files used
+    for the completion flow
+
+```
+abc.constr klayout.lyt klayout_tech.lef lib
+```
+
+-   `logs/sky130hd/ibex/base`
+    Logs directory, which contains log files for each flow stage.
+
+| `logs`                 |                        |                       |
+|------------------------|------------------------|-----------------------|
+| `1_1_yosys.log`        | `3_1_place_gp.log`     | `5_2_route.log` |
+| `2_1_floorplan.log`    | `3_2_place_iop.log`    | `6_1_merge.log`       |
+| `2_2_floorplan_io.log` | `3_3_resizer.log`      | `6_report.log`        |
+| `2_3_tdms_place.log`   | `3_4_opendp.log`       |                       |
+| `2_4_floorplan_macro.log`       | `4_1_cts.log`          |                       |
+| `2_5_floorplan_tapcell.log`      | `4_2_cts_fillcell.log` |                       |
+| `2_6_floorplan_pdn.log`          | `5_1_grt.log`    |                       |
+
+
+-   `results/sky130hd/ibex/base`
+    Results directory which contains `.v/.sdc/.odb/.def/.spef` files
+
+| `results`                   |                         |                    |
+|-----------------------------|-------------------------|--------------------|
+| `1_1_yosys.v`               | `3_1_place_gp.odb`      | `5_route.sdc`      |
+| `1_synth.sdc`               | `3_2_place_iop.odb`     | `6_1_fill.odb`     |
+| `1_synth.v`                 | `3_3_place_resized.odb` | `6_1_fill.sdc`     |
+| `2_1_floorplan.odb`         | `3_4_place_dp.odb`      | `6_1_merged.gds`   |
+| `2_2_floorplan_io.odb`      | `3_place.odb`           | `6_final.odb`      |
+| `2_3_floorplan_tdms.odb`    | `3_place.sdc`           | `6_final.gds`      |
+| `2_4_floorplan_macro.odb`   | `4_1_cts.odb`           | `6_final.sdc`      |
+| `2_5_floorplan_tapcell.odb` | `4_2_cts_fillcell.odb`  | `6_final.spef`     |
+| `2_6_floorplan_pdn.odb`     | `4_cts.odb`             | `6_final.v`        |
+| `2_floorplan.odb`           | `4_cts.sdc`             | `output_guide.mod` |
+| `2_floorplan.sdc`           | `4_cts.v`               | `route.guide`      |
+| `2_floorplan.v`             | `5_route.odb`           | `updated_clks.sdc` |
+
+
+-   `reports/sky130hd/ibex/base`
+    Reports directory, which contains congestion report, DRC
+    report, design statistics and antenna log for reference.
+
+| `reports`         |                     |                        |
+|-------------------|---------------------|------------------------|
+| `congestion.rpt`  | `VDD.rpt`           | `VSS.rpt`              |
+| `5_route_drc.rpt` | `final_clocks.webp` | `final_placement.webp` |
+| `antenna.log`     | `final_clocks.webp` | `final.webp`           |
+| `synth_stat.txt`  | `synth_check.txt`   | `final_resizer.webp`   |
+
+The table below briefly describes the reports directory files.
+
+| File Name              | Description                                              |
+|------------------------|----------------------------------------------------------|
+| `congestion.rpt`       | Gloabl routing congestion if occurred.                   |
+| `5_route_drc.rpt`      | DRC violations if occurred.                              |
+| `final_clocks.webp`    | OR extracted image reference after clock tree synthesis. |
+| `final_resizer.webp`   | OR extracted image reference after resizer.              |
+| `synth_check.txt`      | Synthesis warning/error messages.                        |
+| `antenna.log`          | Antenna check log report.                                |
+| `final_placement.webp` | Extracted image after final placement.                   |
+| `final.webp`           | Extracted image after routing.                           |
+| `synth_stat.txt`       | Post synthesis design statistics log saved here.         |
+
+The flow completes with the message below by creating a merged final GDS file.
+
+```
+[INFO] Writing out GDS/OAS
+'results/sky130hd/ibex/base/6_1_merged.gds'
+cp results/sky130hd/ibex/base/6_1_merged.gds
+results/sky130hd/ibex/base/6_final.gds
+```
+
+## Viewing Results And Logs
+
+OpenROAD-flow-scripts prepends a prefix to each flow stage, as shown below, to
+indicate the position in the RTL-GDS flow. This makes it easier to
+understand and debug each flow stage in case of failure.
+
+View `ibex` design logs:
+
+```shell
+ls logs/sky130hd/ibex/base/
+```
+
+The log structure is as follows:
+
+| `logs`                 |                        |                       |
+|------------------------|------------------------|-----------------------|
+| `1_1_yosys.log`        | `3_1_place_gp.log`     | `5_2_route.log` |
+| `2_1_floorplan.log`    | `3_2_place_iop.log`    | `6_1_merge.log`       |
+| `2_2_floorplan_io.log` | `3_3_resizer.log`      | `6_report.log`        |
+| `2_3_tdms_place.log`   | `3_4_opendp.log`       |                       |
+| `2_4_floorplan_macro.log`       | `4_1_cts.log`          |                       |
+| `2_5_floorplan_tapcell.log`      | `4_2_cts_fillcell.log` |                       |
+| `2_6_floorplan_pdn.log`          | `5_1_grt.log`    |                       |
+
+### Area
+
+View design area and its core utilization:
+
+```
+make gui_final
+report_design_area
+```
+
+View the resulting area as:
+
+```
+Design area 191262 u^2 30% utilization.
+```
+
+### Timing
+
+Users can view flow results using the command interface from the shell or
+the OpenROAD GUI to visualize further and debug. Learn more about the
+[GUI](https://openroad.readthedocs.io/en/latest/main/README.html#gui).
+
+```shell
+make gui_final
+```
+
+Use the following commands in the `Tcl Commands` section of GUI:
+
+```tcl
+report_worst_slack
+report_tns
+report_wns
+```
+
+Note the worst slack, total negative slack and worst negative slack:
+
+```
+worst slack -0.99
+tns -1.29
+wns -0.99
+```
+
+Learn more about visualizing and tracing time paths across the design
+hierarchy refer to the OpenROAD [GUI](https://openroad.readthedocs.io/en/latest/main/README.html#gui).
+
+### Power
+
+Use the report command to view individual power components i.e.
+sequential, combinational, macro and power consumed by I/O pads.
+
+```tcl
+report_power
+```
+
+The power output is as follows:
+
+```
+--------------------------------------------------------------------------
+Group                  Internal  Switching    Leakage      Total
+                          Power      Power      Power      Power
+----------------------------------------------------------------
+Sequential             5.58e-03   6.12e-04   1.67e-08   6.19e-03  19.0%
+Combinational          9.23e-03   1.71e-02   4.90e-08   2.63e-02  81.0%
+Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
+----------------------------------------------------------------
+Total                  1.48e-02   1.77e-02   6.57e-08   3.25e-02 100.0%
+                          45.6%      54.4%       0.0%
+```
+
+## OpenROAD GUI
+
+The GUI allows users to select, control, highlight and navigate the
+design hierarchy and design objects (nets, pins, instances, paths, etc.)
+through detailed visualization and customization options. Find details
+on how to use the [GUI](https://openroad.readthedocs.io/en/latest/main/README.html#gui). All the windows
+aside from the layout are docking windows that can be undocked.  Also it
+can be closed and reopened from the Windows menu.
+
+
+Note:  When you are using remote access, you will need to include -Y (or -X) option in your command to
+enable X11 applications to function properly over the network. By using the command "ssh -Y" followed
+by the remote servers' address or hostname, you can establish a secure connection and activate X11 forwarding.
+This feature enables you to run graphical programs on the remote server and have their windows display
+on your local machines desktop environment.
+
+
+In this section, learn how to:
+
+1. Visualize design hierarchy
+2. Load ODB files for floorplan and layout visualization
+3. Trace the synthesized clock tree to view hierarchy and buffers
+4. Use heat maps to view congestion and observe the effect of placement
+5. View and trace critical timing paths
+6. Set display control options
+7. Zoom to object from inspector
+
+If you have completed the RTL-GDS flow, then proceed to view the final
+GDS file under results directory `./results/sky130hd/ibex/base/`
+
+For the `ibex` design uncomment the `DESIGN_CONFIG`
+variable in the `Makefile` available [here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/Makefile).
+
+```
+# DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk
+DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk
+# DESIGN_CONFIG=./designs/sky130hd/aes/config.mk
+```
+
+```shell
+make gui_final
+```
+
+### Viewing Layout Results
+
+The `make gui_final` command target successively reads and loads the
+technology `.odb` files and the parasitics and invokes the
+GUI in these steps:
+
+-   Reads and loads `.odb` files.
+-   Loads `.spef` (parasitics).
+
+The figure below shows the post-routed DEF for the `ibex` design.
+
+![ibex_final_db](./images/ibex_final_db.webp)
+
+### Visualizing Design Objects And Connectivity
+
+Note the `Display Control` window on the LHS that shows buttons
+for color, visibility and selection options for various design
+objects: Layers, Nets, Instances, Blockages, Heatmaps, etc.
+
+The Inspector window on the RHS allows users to inspect details of
+selected design objects and the timing report.
+
+Try selectively displaying (show/hide) various design objects through
+the display control window and observing their impact on the display.
+
+### Tracing The Clock Tree
+
+View the synthesized clock tree for `ibex` design:
+-   From the top Toolbar Click `Windows` -> `Clock Tree Viewer`
+
+![cts_viewer](./images/CTV_update.webp)
+
+On RHS, click `Clock Tree Viewer` and top right corner, click
+`Update` to view the synthesized clock tree of your design.
+
+View clock tree structure below, the user needs to disable the metal
+`Layers` section on LHS as shown below.
+
+![ibex_clock_tree](./images/ibex_clock_tree.webp)
+
+From the top Toolbar, click on the `Windows` menu to select/hide different
+view options of Scripting, Display control, etc.
+
+### Using Heat Maps
+
+From the Menu Bar, Click on `Tools` -> `Heat Maps` -> `Placement Density` to view
+congestion selectively on vertical and horizontal layers.
+
+Expand `Heat Maps` -> `Placement Density` from the Display Control window
+available on LHS of OpenROAD GUI.
+
+View congestion on all layers between 50-100%:
+
+In the `Placement density` setup pop-up window, Select `Minimum` -> `50.00%`
+`Maximum` -> `100.00%`
+
+![placement_heat_map](./images/placement_heatmap.webp)
+
+From `Display Control`, select `Heat Maps` -> `Routing Congestion` as
+follows:
+
+![routing_heat_map](./images/routing_heatmap.webp)
+
+From `Display Control`, select `Heat Maps` -> `Power Density` as
+follows:
+
+![power_heat_map](./images/power_heatmap.webp)
+
+### Viewing Timing Report
+
+Click `Timing` -> `Options` to view and traverse specific timing paths.
+From Toolbar, click on the `Timing` icon, View `Timing Report` window added
+at the right side (RHS) of GUI as shown below.
+
+![Timing report option](./images/ibex_final_db.webp)
+
+In `Timing Report` Select `Paths` -> `Update`, `Paths` should be integer
+numbers. The number of timing paths should be displayed in the current
+window as follows:
+
+![Clock Path Update](./images/clock_path_update.webp)
+
+Select `Setup` or `Hold` tabs and view required arrival times and
+slack for each timing path segment.
+
+For each `Setup` or `Hold` path group, path details have a specific `pin
+name, Time, Delay, Slew and Load` value with the clock to register, register
+to register and register to output data path.
+
+### Using Rulers
+
+A ruler can measure the distance between any two objects in the design or
+metal layer length and width to be measured, etc.
+
+Example of how to measure the distance between VDD and VSS power grid click on:
+
+`Tools` -> `Ruler K`
+
+![Ruler Tool](./images/ruler_tool.png)
+
+Distance between VDD and VSS layer is `11.970`
+
+### DRC Viewer
+
+You can use the GUI to trace DRC violations and fix them.
+
+View DRC violations post routing:
+
+```shell
+less ./reports/sky130hd/ibex/base/5_route_drc.rpt
+```
+
+Any DRC violations are logged in the `5_route_drc.rpt` file, which is
+empty otherwise.
+
+From OpenROAD GUI, Enable the menu options `Windows` -> `DRC Viewer`. A
+`DRC viewer` window is added on the right side (RHS) of the GUI. From
+`DRC Viewer` -> `Load` navigate to `5_route_drc.rpt`
+
+![DRC Report Load](./images/drc_report_load.webp)
+
+By selecting DRC violation details, designers can analyze and fix them. Here
+user will learn how a DRC violation can be traced with the `gcd` design. Refer
+to the following OpenROAD test case for more details.
+
+```shell
+cd ./flow/tutorials/scripts/drt/
+openroad -gui
+```
+
+In the `Tcl Commands` section of GUI:
+
+```tcl
+source drc_issue.tcl
+```
+
+Post detail routing in the log, you can find the number of violations left
+in the design:
+
+```
+[INFO DRT-0199] Number of violations = 7.
+```
+
+Based on `DRC Viewer` steps load `results/5_route_drc.rpt`. GUI as
+follows
+
+![gcd DRC issue load](./images/gcd_drc_issue.webp)
+
+`X mark` in the design highlights DRC violations.
+
+From `DRC Viewer` on RHS `expand` -> `Short`
+
+This shows the number of `violations` in the design. Zoom the design
+for a clean view of the violation:
+
+![View DRC Violation](./images/view_violation.webp)
+
+`output53` has overlaps and this causes the `short violation`.
+
+Open the input DEF file `drc_cts.def` to check the source of the
+overlap.
+
+Note the snippet of DEF file where `output51` and `output53` have
+the same placed coordinates and hence cause the placement violation.
+
+```
+- output51 sky130_fd_sc_hd__clkbuf_1 + PLACED ( 267260 136000 ) N ;
+- output53 sky130_fd_sc_hd__clkbuf_1 + PLACED ( 267260 136000 ) N ;
+```
+
+Use the test case provided in `4_cts.def` with the changes applied for
+updated coordinates as follows:
+
+```
+- output51 sky130_fd_sc_hd__clkbuf_1 + PLACED ( 267260 136000 ) N ;
+- output53 sky130_fd_sc_hd__clkbuf_1 + PLACED ( 124660 266560 ) N ;
+```
+
+Close the current GUI and re-load the GUI with the updated DEF to see
+fixed DRC violation in the design:
+
+```shell
+openroad -gui
+source drc_fix.tcl
+```
+
+In the post detail routing log, the user can find the number of violations
+left in the design:
+
+```
+[INFO DRT-0199] Number of violations = 0.
+```
+
+Routing completed with 0 violations.
+
+### Tcl Command Interface
+
+Execute OpenROAD-flow-scripts Tcl commands from the GUI. Type `help`
+to view Tcl Commands available. In OpenROAD GUI, at the bottom,
+`TCL commands` executable space is available to run the commands.
+For example
+
+View `design area`:
+
+```tcl
+report_design_area
+```
+
+Try the below timing report commands to view timing results interactively:
+
+```tcl
+report_wns
+report_tns
+report_worst_slack
+```
+
+### Customizing The GUI
+
+Customize the GUI by creating your own widgets such as menu bars,
+toolbar buttons, dialog boxes, etc.
+
+Refer to the [GUI](https://openroad.readthedocs.io/en/latest/main/README.html#gui).
+
+Create `Load_LEF` toolbar button in GUI to automatically load
+specified `.lef` files.
+
+```shell
+openroad -gui
+```
+
+![Default GUI](./images/default_gui.webp)
+
+To view `load_lef.tcl`, run the command:
+
+```shell
+less ./flow/tutorials/scripts/gui/load_lef.tcl
+```
+
+```tcl
+proc load_lef_sky130 {} {
+    set FLOW_PATH [exec pwd]
+    read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
+    read_lef $FLOW_PATH/../../../platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
+}
+create_toolbar_button -name "Load_LEF" -text "Load_LEF" -script {load_lef_sky130} -echo
+```
+
+From OpenROAD GUI `Tcl commands`:
+
+```tcl
+cd ./flow/tutorials/scripts/gui/
+source load_lef.tcl
+```
+
+`Load_LEF` toolbar button added as follows:
+
+![Load LEF toolbar button](./images/Load_LEF_button.webp)
+
+From Toolbar menus, Click on `Load_LEF.` This loads the specified `sky130`
+technology `.tlef` and `merged.lef` file in the current OpenROAD GUI
+as follows:
+
+![sky130 LEF file load](./images/sky130_lef_load.webp)
+
+## Understanding and Analyzing OpenROAD Flow Stages and Results
+
+The OpenROAD flow is fully automated and yet the user can usefully intervene
+to explore, analyze and optimize your design flow for good PPA.
+
+In this section, you will learn specific details of flow stages and
+learn to explore various design configurations and optimizations to
+target specific design goals, i.e., PPA (area, timing, power).
+
+### Synthesis Explorations
+
+#### Area And Timing Optimization
+
+Explore optimization options using synthesis options: `ABC_AREA` and `ABC_SPEED`.
+
+Set `ABC_AREA=1` for area optimization and `ABC_SPEED=1` for timing optimization.
+Update design `config.mk` for each case and re-run the flow to view impact.
+
+To view `ibex` design [config.mk](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/sky130hd/ibex/config.mk).
+
+```
+#Synthesis strategies
+export ABC_AREA = 1
+```
+
+Run `make` command from `flow` directory as follows:
+
+```shell
+make DESIGN_CONFIG=./designs/sky130hd/gcd/config.mk
+```
+
+The `gcd` design synthesis results for area and speed optimizations are shown below:
+
+| Synthesis Statistics  | ABC_SPEED                            | ABC_AREA                             |
+|-----------------------|--------------------------------------|--------------------------------------|
+| `Number of wires`     | 224                                  | 224                                  |
+| `Number of wire bits` | 270                                  | 270                                  |
+| `Number of cells`     | 234                                  | 234                                  |
+| `Chip area`           | 2083.248000                          | 2083.248000                          |
+| `Final Design Area`   | Design area 4295 u^2 6% utilization. | Design area 4074 u^2 6% utilization. |
+
+Note: Results for area optimization should be ideally checked after
+floorplanning to verify the final impact. First, relax the `.sdc` constraint
+and re-run to see area impact. Otherwise, the repair design command will
+increase the area to meet timing regardless of the netlist produced earlier.
+
+### Floorplanning
+
+This section describes OpenROAD-flow-scripts floorplanning and
+placement functions using the GUI.
+
+#### Floorplan Initialization Based On Core And Die Area
+
+Refer to the following OpenROAD built-in examples
+[here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/ifp/test/init_floorplan1.tcl).
+
+Run the following commands in the terminal in OpenROAD tool root directory to build and view the created
+floorplan.
+
+```shell
+cd ../tools/OpenROAD/src/ifp/test/
+openroad -gui
+```
+
+In `Tcl Commands` section GUI:
+
+```tcl
+source init_floorplan1.tcl
+```
+
+View the resulting die area "0 0 1000 1000" and core area "100 100 900 900"
+in microns shown below:
+
+![Absolute Floorplan](./images/absolute_die.webp)
+
+#### Floorplan Based On Core Utilization
+
+Refer to the following OpenROAD built-in examples
+[here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/ifp/test/init_floorplan2.tcl).
+
+Run the following commands in the terminal in OpenROAD tool root directory to view how the floorplan
+initialized:
+
+```shell
+cd ../tools/OpenROAD/src/ifp/test/
+openroad -gui
+```
+
+In the `Tcl Commands` section of the GUI:
+
+```tcl
+source init_floorplan2.tcl
+```
+
+View the resulting core utilization of 30 created following floorplan:
+
+![Relative Floorplan](./images/core_util.webp)
+
+### IO Pin Placement
+
+Place pins on the boundary of the die on the track grid to minimize net
+wirelengths. Pin placement also creates a metal shape for each pin using
+min-area rules.
+
+For designs with unplaced cells, the net wirelength is computed considering
+the center of the die area as the unplaced cells position.
+
+Find pin placement document [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/ppl/README.md).
+
+Refer to the built-in examples [here](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/ppl/test).
+
+Launch openroad GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/ppl/test/
+openroad -gui
+```
+
+Run [place_pin4.tcl](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/ppl/test/place_pin4.tcl) script to view
+pin placement.
+
+From the GUI `Tcl commands` section:
+
+```tcl
+source place_pin4.tcl
+```
+
+View the resulting pin placement in GUI:
+
+![place_pin](./images/place_pin.webp)
+
+In OpenROAD GUI to enlarge `clk` pin placement, hold mouse right button
+as follows and draw sqaure box in specific location:
+
+![pin_zoom](./images/pin_zoom_RC.webp)
+
+Now `clk` pin zoom to clear view as follows:
+
+![pin_zoomed](./images/pin_zoomed.webp)
+
+
+### Chip Level IO Pad Placement
+
+In this section, you will generate an I/O pad ring for the `coyote` design
+using a Tcl script.
+
+ICeWall is a utility to place IO cells around the periphery of a design,
+and associate the IO cells with those present in the netlist of the
+design.
+
+For I/O pad placement using ICeWall refer to the readme file
+[here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pad/README.md).
+
+Refer to the built-in examples [here](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/pad/test).
+
+Launch openroad GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/pad/test/
+openroad -gui
+```
+
+Run [skywater130_coyote_tc.tcl](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pad/test/skywater130_coyote_tc.tcl) script
+to view IO pad placement.
+
+From the GUI `Tcl commands` section:
+
+```tcl
+source skywater130_coyote_tc.tcl
+```
+
+View the resulting IO pad ring in GUI:
+
+![coyote pad ring](./images/coyote_pad_ring.webp)
+
+### Power Planning And Analysis
+
+In this section, you will use the design `gcd` to create a
+power grid and run power analysis.
+
+Pdngen is used for power planning. Find the document [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pdn/README.md).
+
+Refer to the built-in examples [here](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/pdn/test).
+
+Launch openroad GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/pdn/test
+openroad -gui
+```
+
+Run [core_grid_snap.tcl](.(https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pdn/test/core_grid_snap.tcl)
+to generate power grid for `gcd` design.
+
+```tcl
+source core_grid_snap.tcl
+```
+View the resulting power plan for `gcd` design:
+
+![gcd PDN GUI](./images/gcd_pdn_gui.webp)
+
+#### IR Drop Analysis
+IR drop is the voltage drop in the metal wires constituting the power
+grid before it reaches the power pins of the standard cells. It becomes
+very important to limit the IR drop as it affects the speed of the cells
+and overall performance of the chip.
+
+PDNSim is an open-source static IR analyzer.
+
+Features:
+
+-   Report worst IR drop.
+-   Report worst current density over all nodes and wire segments in
+    the power distribution network, given a placed and PDN-synthesized design.
+-   Check for floating PDN stripes on the power and ground nets.
+-   Spice netlist writer for power distribution network wire segments.
+
+Refer to the built-in examples [here](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/psm/test).
+
+Launch openroad by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/psm/test
+openroad
+```
+
+Run [gcd_test_vdd.tcl](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/psm/test/gcd_test_vdd.tcl)
+to generate IR drop report for `gcd` design.
+
+```tcl
+source gcd_test_vdd.tcl
+```
+
+Find the IR drop report at the end of the log as follows:
+```
+########## IR report #################
+Worstcase voltage: 1.10e+00 V
+Average IR drop  : 1.68e-04 V
+Worstcase IR drop: 2.98e-04 V
+######################################
+```
+
+### Tapcell insertion
+
+Tap cells are non-functional cells that can have a well tie, substrate
+tie or both. They are typically used when most or all of the standard
+cells in the library contain no substrate or well taps. Tap cells help
+tie the VDD and GND levels and thereby prevent drift and latch-up.
+
+The end cap cell or boundary cell is placed at both the ends of each
+placement row to terminate the row. They protect the standard cell
+gate at the boundary from damage during manufacturing.
+
+Tap cells are placed after the macro placement and power rail creation.
+This stage is called the pre-placement stage. Tap cells are placed in a
+regular interval in each row of placement. The maximum distance between
+the tap cells must be as per the DRC rule of that particular technology library.
+
+The figures below show two examples of tapcell insertion. When only the
+`-tapcell_master` and `-endcap_master` masters are given, the tapcell placement
+is similar to Figure 1. When the remaining masters are give, the tapcell
+placement is similar to Figure 2.
+
+Refer to the GUI figures to highlight well tap and end cap cells. The image
+does not differentiate and just shows a bunch of rectangles.
+
+| <img src="./images/tapcell_example1.svg" width=450px> | <img src="./images/tapcell_example2.svg" width=450px> |
+|:--:|:--:|
+| Figure 1: Tapcell insertion representation | Figure 2:  Tapcell insertion around macro representation |
+
+Refer to the following built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/tap/test/gcd_nangate45.tcl)
+to learn about Tap/endcap cell insertion.
+
+To view this in OpenROAD GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/tap/test/
+openroad -gui
+```
+
+In the `Tcl Commands` section of GUI
+
+```tcl
+source gcd_nangate45.tcl
+```
+
+View the resulting tap cell insertion as follows:
+
+![Tap_Cell_Insertion](./images/tapcell_insertion_view.webp)
+
+### Tie Cells
+
+The tie cell is a standard cell, designed specially to provide the high
+or low signal to the input (gate terminal) of any logic gate.
+Where ever netlist is having any pin connected to 0 logic or 1 logic
+(like .A(1'b0) or .IN(1'b1), a tie cell gets inserted there.
+
+Refer to the following built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/ifp/test/tiecells.tcl)
+to learn about Tie cell insertion.
+
+To check this in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/ifp/test/
+openroad
+source tiecells.tcl
+```
+
+Refer the following verilog code which have tie high/low net.
+[here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/ifp/test/tiecells.v)
+```
+AND2_X1 u2 (.A1(r1q), .A2(1'b0), .ZN(u2z0));
+AND2_X1 u3 (.A1(u1z), .A2(1'b1), .ZN(u2z1));
+```
+With following `insert_tiecells` command:
+```
+insert_tiecells LOGIC0_X1/Z -prefix "TIE_ZERO_"
+insert_tiecells LOGIC1_X1/Z
+```
+During floorplan stage, those nets converted to tiecells as follows
+based on library(This is Nangate45 specific):
+```
+[INFO IFP-0030] Inserted 1 tiecells using LOGIC0_X1/Z.
+[INFO IFP-0030] Inserted 1 tiecells using LOGIC1_X1/Z.
+```
+
+### Macro or Standard Cell Placement
+
+#### Macro Placement
+
+In this section, you will explore various placement options for macros
+and standard cells and study the impact on area and timing.
+
+Refer to the following built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/gpl/test/macro01.tcl)
+to learn about macro placement.
+
+Placement density impacts how widely standard cells are placed in the
+core area. To view this in OpenROAD GUI run the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/gpl/test/
+openroad -gui
+```
+
+In the `Tcl Commands` section of GUI
+
+```tcl
+source macro01.tcl
+```
+
+Read the resulting macro placement with a complete core view:
+
+| <img src="./images/macro_place_full_view.webp" width=450px> | <img src="./images/macro_place_close_view.webp" width=450px> |
+|:--:|:--:|
+| Figure 1: With density 0.7 | Figure 2: Zoomed view of macro and std cell placement|
+
+Reduce the placement density and observe the impact on placement, by
+running below command in `Tcl Commands` section of GUI:
+
+```tcl
+global_placement -density 0.6
+```
+
+Read the resulting macro placement with a complete core view:
+
+| <img src="./images/placement_density_06_full.webp" width=450px> | <img src="./images/placement_density_06_zoomed.webp" width=450px> |
+|:--:|:--:|
+| Figure 1: With density 0.6 | Figure 2: Zoomed view of macro and std cell placement |
+
+##### Macro Placement With Halo Spacing
+
+Explore macro placement with halo spacing, refer to the example
+[here]((https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/mpl/test/).
+
+Launch GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+```shell
+cd ../tools/OpenROAD/src/mpl/test
+openroad -gui
+```
+
+In the `Tcl Commands` section of GUI:
+
+```tcl
+source helpers.tcl
+source level3.tcl
+global_placement
+```
+
+DEF file without halo spacing
+
+![gcd without halo spacing](./images/without_halo.webp)
+
+Now increase the halo width for better routing resources.
+
+In the `Tcl Commands` section of GUI:
+
+```tcl
+macro_placement -halo {0.5 0.5}
+```
+
+Overlapping macros placed `0.5` micron H/V halo around macros.
+
+![gcd with halo spacing](./images/with_halo.webp)
+
+#### Defining Placement Density
+
+To learn on placement density strategies for `ibex` design, go to
+`OpenROAD-flow-scripts/flow`. Type:
+
+```shell
+openroad -gui
+```
+
+Enter the following commands in the `Tcl Commands` section of GUI
+
+```tcl
+read_lef ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
+read_lef ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
+read_def ./results/sky130hd/ibex/base/3_place.def
+```
+![ibex placement density 60](./images/ibex_pl_60.webp)
+
+Change `CORE_UTILIZATION` and `PLACE_DENSITY` for the `ibex` design
+`config.mk` as follows.
+
+View `ibex` design `config.mk`
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/sky130hd/ibex/config.mk).
+
+```
+export CORE_UTILIZATION = 40
+export PLACE_DENSITY_LB_ADDON = 0.1
+```
+
+Re-run the `ibex` design with the below command:
+
+```shell
+make DESIGN_CONFIG=./designs/sky130hd/ibex/config.mk
+```
+
+View the `ibex` design placement density heat map as shown below:
+
+![ibex placement density 50](./images/ibex_pl_50.webp)
+
+So from above, GUI understood that change in `CORE_UTILIZATION` from 20
+to 40 and placement density default 0.60 to 0.50 changes standard cell
+placement became widely spread.
+
+### Timing Optimizations
+
+#### Timing Optimization Using repair_design
+
+The `repair_design` command inserts buffers on nets to repair `max
+slew, max capacitance and max fanout` violations and on long wires to
+reduce RC delay. It also resizes gates to normalize slews. Use
+`estimate_parasitics -placement` before `repair_design` to account
+for estimated post-placement parasitics.
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/rsz/test/repair_slew1.tcl).
+
+Launch GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/rsz/test/
+openroad -gui
+```
+
+Copy and paste the below commands in the `Tcl Commands` section of GUI.
+
+```tcl
+source "helpers.tcl"
+source "hi_fanout.tcl"
+read_liberty Nangate45/Nangate45_typ.lib
+read_lef Nangate45/Nangate45.lef
+set def_file [make_result_file "repair_slew1.def"]
+write_hi_fanout_def $def_file 30
+read_def $def_file
+
+create_clock -period 1 clk1
+set_wire_rc -layer metal3
+
+estimate_parasitics -placement
+set_max_transition .05 [current_design]
+
+puts "Found [sta::max_slew_violation_count] violations"
+```
+
+The number of violations log as:
+
+```
+Found 31 violations
+```
+
+These violations were fixed by:
+
+```tcl
+repair_design
+```
+
+The log is as follows:
+
+```
+[INFO RSZ-0058] Using max wire length 853um.
+[INFO RSZ-0039] Resized 1 instance.
+```
+
+To view violation counts again:
+
+```tcl
+puts "Found [sta::max_slew_violation_count] violations"
+```
+
+The log follows:
+
+```
+Found 0 violations
+```
+
+`repair_design` fixed all 31 violations.
+
+#### Timing Optimization Using repair_timing
+
+The `repair_timing` command repairs setup and hold violations. It was
+run after clock tree synthesis with propagated clocks.
+
+While repairing hold violations, buffers are not inserted since that may
+cause setup violations unless '-allow_setup_violations' is specified.
+Use `-slack_margin` to add additional slack margin.
+
+#### Timing Optimization Based On Multiple Corners
+
+OpenROAD supports multiple corner analysis to calculate worst-case setup
+and hold violations.
+
+Setup time optimization is based on the slow corner or the best case when
+the launch clock arrives later than the data clock.
+Hold time optimization is based on the fast corner or the best case when
+the launch clock arrives earlier than the capture clock.
+
+Refer to the following `gcd` design on `repair_timing` with fast and slow
+corners.
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/test/gcd_sky130hd_fast_slow.tcl).
+
+Run the following commands in the terminal:
+```shell
+cd ../../test/
+openroad
+source gcd_sky130hd_fast_slow.tcl
+```
+
+The resulting `worst slack`, `TNS`:
+
+```
+report_worst_slack -min -digits 3
+worst slack 0.321
+report_worst_slack -max -digits 3
+worst slack -16.005
+report_tns -digits 3
+tns -529.496
+```
+
+#### Fixing Setup Violations
+
+To fix setup timing path violations, use `repair_timing -setup.`
+
+Refer to the following built-in example to learn more about fixing setup
+timing violations.
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/rsz/test/repair_setup4.tcl).
+
+Launch OpenROAD in an interactive mode by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/rsz/test/
+openroad
+```
+
+Copy and paste the following Tcl commands.
+
+```tcl
+define_corners fast slow
+read_liberty -corner slow Nangate45/Nangate45_slow.lib
+read_liberty -corner fast Nangate45/Nangate45_fast.lib
+read_lef Nangate45/Nangate45.lef
+read_def repair_setup1.def
+create_clock -period 0.3 clk
+set_wire_rc -layer metal3
+estimate_parasitics -placement
+report_checks -fields input -digits 3
+```
+
+View the generated timing report with the slack violation.
+
+```
+Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
+Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
+Path Group: clk
+Path Type: max
+Corner: slow
+
+   Delay     Time   Description
+-----------------------------------------------------------
+   0.000    0.000   clock clk (rise edge)
+   0.000    0.000   clock network delay (ideal)
+   0.000    0.000 ^ r1/CK (DFF_X1)
+   0.835    0.835 ^ r1/Q (DFF_X1)
+   0.001    0.836 ^ u1/A (BUF_X1)
+   0.196    1.032 ^ u1/Z (BUF_X1)
+   0.001    1.033 ^ u2/A (BUF_X1)
+   0.121    1.154 ^ u2/Z (BUF_X1)
+   0.001    1.155 ^ u3/A (BUF_X1)
+   0.118    1.273 ^ u3/Z (BUF_X1)
+   0.001    1.275 ^ u4/A (BUF_X1)
+   0.118    1.393 ^ u4/Z (BUF_X1)
+   0.001    1.394 ^ u5/A (BUF_X1)
+   0.367    1.761 ^ u5/Z (BUF_X1)
+   0.048    1.809 ^ r2/D (DFF_X1)
+            1.809   data arrival time
+
+   0.300    0.300   clock clk (rise edge)
+   0.000    0.300   clock network delay (ideal)
+   0.000    0.300   clock reconvergence pessimism
+            0.300 ^ r2/CK (DFF_X1)
+  -0.155    0.145   library setup time
+            0.145   data required time
+-----------------------------------------------------------
+            0.145   data required time
+           -1.809   data arrival time
+-----------------------------------------------------------
+           -1.664   slack (VIOLATED)
+
+```
+
+Fix setup violation using:
+
+```tcl
+repair_timing -setup
+```
+
+The log is as follows:
+
+```
+[INFO RSZ-0040] Inserted 4 buffers.
+[INFO RSZ-0041] Resized 16 instances.
+[WARNING RSZ-0062] Unable to repair all setup violations.
+```
+
+Reduce the clock frequency by increasing the clock period to `0.9` and re-run
+`repair_timing` to fix the setup violation warnings. Such timing violations
+are automatically fixed by the `resizer` `post CTS` and `global routing.`
+
+```yvl
+create_clock -period 0.9 clk
+repair_timing -setup
+```
+
+To view timing logs post-repair timing, type:
+
+```tcl
+report_checks -fields input -digits 3
+```
+
+The log is as follows:
+
+```
+Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
+Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
+Path Group: clk
+Path Type: max
+Corner: slow
+
+   Delay     Time   Description
+-----------------------------------------------------------
+   0.000    0.000   clock clk (rise edge)
+   0.000    0.000   clock network delay (ideal)
+   0.000    0.000 ^ r1/CK (DFF_X1)
+   0.264    0.264 v r1/Q (DFF_X1)
+   0.002    0.266 v u1/A (BUF_X4)
+   0.090    0.356 v u1/Z (BUF_X4)
+   0.003    0.359 v u2/A (BUF_X8)
+   0.076    0.435 v u2/Z (BUF_X8)
+   0.003    0.438 v u3/A (BUF_X8)
+   0.074    0.512 v u3/Z (BUF_X8)
+   0.003    0.515 v u4/A (BUF_X8)
+   0.077    0.592 v u4/Z (BUF_X8)
+   0.005    0.597 v u5/A (BUF_X16)
+   0.077    0.674 v u5/Z (BUF_X16)
+   0.036    0.710 v r2/D (DFF_X1)
+            0.710   data arrival time
+
+   0.900    0.900   clock clk (rise edge)
+   0.000    0.900   clock network delay (ideal)
+   0.000    0.900   clock reconvergence pessimism
+            0.900 ^ r2/CK (DFF_X1)
+  -0.172    0.728   library setup time
+            0.728   data required time
+-----------------------------------------------------------
+            0.728   data required time
+           -0.710   data arrival time
+-----------------------------------------------------------
+            0.019   slack (MET)
+```
+
+#### Fixing Hold Violations
+
+To fix hold violation for the design, command to use `repair_timing
+-hold`
+
+Refer to the example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/rsz/test/repair_hold10.tcl)
+to learn more about fixing hold violations.
+
+Check hold violation post-global routing using the following Tcl
+commands. Run below steps in terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/rsz/test/
+openroad -gui
+```
+
+Copy and paste the below commands in the `Tcl Commands` section of GUI.
+
+```tcl
+source helpers.tcl
+read_liberty sky130hd/sky130hd_tt.lib
+read_lef sky130hd/sky130hd.tlef
+read_lef sky130hd/sky130hd_std_cell.lef
+read_def repair_hold10.def
+create_clock -period 2 clk
+set_propagated_clock clk
+set_wire_rc -resistance 0.0001 -capacitance 0.00001
+set_routing_layers -signal met1-met5
+global_route
+estimate_parasitics -global_routing
+report_worst_slack -min
+```
+
+Read the resulting worst slack as:
+
+```
+worst slack -1.95
+```
+
+The above worst slack was fixed with:
+
+```tcl
+repair_timing -hold
+```
+
+The log is as follows:
+
+```
+[INFO RSZ-0046] Found 2 endpoints with hold violations.
+[INFO RSZ-0032] Inserted 5 hold buffers.
+```
+
+Re-check the slack value after repair_timing. Type:
+
+```tcl
+report_worst_slack -min
+```
+
+The result worst slack value is as follows:
+
+```
+worst slack 0.16
+```
+
+Note that the worst slack is now met and the hold violation was fixed by
+the resizer.
+
+### Clock Tree Synthesis
+
+To perform clock tree synthesis `clock_tree_synthesis` flow command used.
+The OpenROAD-flow-scripts automatically generates a well-balanced clock tree post-placement.
+In this section, you will learn details about the building and visualize the
+clock tree.
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/cts/test/simple_test.tcl).
+
+Launch OpenROAD GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/cts/test/
+openroad -gui
+```
+
+To build the clock tree, run the following commands in `Tcl Commands` of
+GUI:
+
+```tcl
+read_lef Nangate45/Nangate45.lef
+read_liberty Nangate45/Nangate45_typ.lib
+read_def "16sinks.def"
+create_clock -period 5 clk
+set_wire_rc -clock -layer metal3
+clock_tree_synthesis -root_buf CLKBUF_X3 \
+                     -buf_list CLKBUF_X3 \
+                     -wire_unit 20
+```
+
+Layout view before CTS as follows:
+
+![Layout before CTS](./images/Layout_before_CTS.webp)
+
+Layout view after CTS can be viewed with `Update` option.
+
+![Layout after CTS](./images/Layout_after_CTS.webp)
+
+Here we explore how clock tree buffers are inserted to balance the clock
+tree structure.
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/cts/test/balance_levels.tcl).
+
+Generate a clock- tree that is unbalanced first, then explore the
+creation of a well-balanced clock tree.
+
+Launch OpenROAD GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/cts/test/
+openroad -gui
+```
+
+Use the following commands in the `TCL commands` section of GUI:
+
+```tcl
+source "helpers.tcl"
+source "cts-helpers.tcl"
+read_liberty Nangate45/Nangate45_typ.lib
+read_lef Nangate45/Nangate45.lef
+set block [make_array 300 200000 200000 150]
+sta::db_network_defined
+create_clock -period 5 clk
+set_wire_rc -clock -layer metal5
+```
+
+The clock tree structure is as follows with unbalanced mode.
+
+![Unbalanced Clock tree](./images/unbalanced_clock_tree.webp)
+
+Use the `clock_tree_synthesis` command to balance this clock tree structure
+with buffers. See the format as follows.
+
+```tcl
+clock_tree_synthesis -root_buf CLKBUF_X3 \
+                     -buf_list CLKBUF_X3 \
+                     -wire_unit 20 \
+                     -post_cts_disable \
+                     -sink_clustering_enable \
+                     -distance_between_buffers 100 \
+                     -sink_clustering_size 10 \
+                     -sink_clustering_max_diameter 60 \
+                     -balance_levels \
+                     -num_static_layers 1
+```
+
+To view the balanced clock tree after CTS, in GUI Toolbar, select
+
+`Clock Tree Viewer` and click `Update` to view the resulting clock
+tree in GUI as follows:
+
+![Balanced Clock Tree](./images/balanced_clock_tree.webp)
+
+#### Reporting Clock Skews
+
+The OpenROAD-flow-scripts flow automatically fixes any skew issues that could potentially
+cause hold violations downstream in the timing path.
+
+```tcl
+report_clock_skew
+```
+
+For the `ibex` design, refer to the following logs to view clock skew reports.
+
+```shell
+less logs/sky130hd/ibex/base/4_1_cts.log
+```
+
+```
+cts pre-repair report_clock_skew
+--------------------------------------------------------------------------
+Clock core_clock
+Latency      CRPR       Skew
+_28453_/CLK ^
+   5.92
+_29312_/CLK ^
+   1.41      0.00       4.51
+```
+
+```
+cts post-repair report_clock_skew
+--------------------------------------------------------------------------
+Clock core_clock
+Latency      CRPR       Skew
+_28453_/CLK ^
+   5.92
+_29312_/CLK ^
+   1.41      0.00       4.51
+```
+
+```
+cts final report_clock_skew
+--------------------------------------------------------------------------
+Clock core_clock
+Latency      CRPR       Skew
+_27810_/CLK ^
+   5.97
+_29266_/CLK ^
+   1.41      0.00       4.56
+```
+
+#### Reporting CTS Metrics
+
+Run `report_cts` command to view useful metrics such as number of clock
+roots, number of buffers inserted, number of clock subnets and number of
+sinks.
+
+Refer to the built-in examples [here](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/cts/test).
+
+Run these Tcl commands in the terminal in OpenROAD tool root directory:
+
+```
+cd ../tools/OpenROAD/src/cts/test/
+openroad
+source post_cts_opt.tcl
+report_cts
+```
+
+CTS metrics are as follows for the current design.
+
+```
+[INFO CTS-0003] Total number of Clock Roots: 1.
+[INFO CTS-0004] Total number of Buffers Inserted: 35.
+[INFO CTS-0005] Total number of Clock Subnets: 35.
+[INFO CTS-0006] Total number of Sinks: 301.
+```
+
+### Adding Filler Cells
+
+Filler cells fills gaps between detail-placed instances to connect the
+power and ground rails in the rows. Filler cells have no logical
+connectivity. These cells are provided continuity in the rows for VDD
+and VSS nets and it also contains substrate nwell connection to improve
+substrate biasing.
+
+`filler_masters` is a list of master/macro names to use for
+filling the gaps.
+
+Refer to the following built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/dpl/test/fillers1.tcl)
+to learn about filler cell insertion.
+
+To view this in OpenROAD GUI run the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/grt/test/
+openroad -gui
+```
+
+In the `Tcl Commands` section of GUI,run following commands:
+
+```tcl
+source "helpers.tcl"
+read_lef "Nangate45/Nangate45.lef"
+read_def "gcd.def"
+```
+
+Loaded DEF view without filler insertion:
+
+![Without_Fill_Cell_Insertion](./images/wo_fillcell_insertion.webp)
+
+Run following commands for filler cell insertion:
+```
+set filler_master [list FILLCELL_X1 FILLCELL_X2 FILLCELL_X4 FILLCELL_X8 FILLCELL_X16]
+filler_placement $filler_master
+```
+
+View the resulting fill cell insertion as follows:
+
+![Fill_Cell_Insertion](./images/fillcell_insertion.webp)
+
+Filler cells removed with `remove_fillers` command.
+
+### Global Routing
+
+The global router analyzes available routing resources and automatically
+allocates them to avoid any  H/V  overflow violations for optimal routing. 
+It generates a congestion report for GCells showing total resources, demand,
+utilization, location and the H/V violation status. If there are no violations
+reported then the design can proceed to detail routing.
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/grt/test/gcd.tcl).
+
+Launch OpenROAD GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/grt/test/
+openroad -gui
+```
+
+To run the global routing, run the following commands in `Tcl Commands` of
+GUI:
+
+```tcl
+source gcd.tcl
+```
+
+Routing resource and congestion analysis done with below log:
+```
+[INFO GRT-0096] Final congestion report:
+Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
+---------------------------------------------------------------------------------------
+metal1           31235          1651            5.29%             0 /  0 /  0
+metal2           24628          1652            6.71%             0 /  0 /  0
+metal3           33120            40            0.12%             0 /  0 /  0
+metal4           15698             0            0.00%             0 /  0 /  0
+metal5           15404             0            0.00%             0 /  0 /  0
+metal6           15642             0            0.00%             0 /  0 /  0
+metal7            4416             0            0.00%             0 /  0 /  0
+metal8            4512             0            0.00%             0 /  0 /  0
+metal9            2208             0            0.00%             0 /  0 /  0
+metal10           2256             0            0.00%             0 /  0 /  0
+---------------------------------------------------------------------------------------
+Total           149119          3343            2.24%             0 /  0 /  0
+
+[INFO GRT-0018] Total wirelength: 10598 um
+[INFO GRT-0014] Routed nets: 563
+```
+
+View the resulting global routing in GUI as follows:
+
+![Global Route](./images/global_route_gcd.webp)
+
+### Detail Routing
+
+TritonRoute is an open-source detailed router for modern industrial designs.
+The router consists of several main building blocks, including pin access
+analysis, track assignment, initial detailed routing, search and repair, and a DRC engine.
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/drt/test/gcd_nangate45.tcl).
+
+Launch OpenROAD GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/drt/test/
+openroad -gui
+```
+
+To run the detail routing, run the following commands in `Tcl Commands` of
+GUI:
+
+```tcl
+read_lef Nangate45/Nangate45_tech.lef
+read_lef Nangate45/Nangate45_stdcell.lef
+read_def gcd_nangate45_preroute.def
+read_guides gcd_nangate45.route_guide
+set_thread_count [expr [exec getconf _NPROCESSORS_ONLN] / 4]
+detailed_route -output_drc results/gcd_nangate45.output.drc.rpt \
+               -output_maze results/gcd_nangate45.output.maze.log \
+               -verbose 1
+write_db gcd_nangate45.odb
+```
+
+For successful routing, DRT will end with 0 violations.
+
+Log as follows:
+
+```
+[INFO DRT-0199]   Number of violations = 0.
+[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 674.22 (MB), peak = 686.08 (MB)
+Total wire length = 5680 um.
+Total wire length on LAYER metal1 = 19 um.
+Total wire length on LAYER metal2 = 2798 um.
+Total wire length on LAYER metal3 = 2614 um.
+Total wire length on LAYER metal4 = 116 um.
+Total wire length on LAYER metal5 = 63 um.
+Total wire length on LAYER metal6 = 36 um.
+Total wire length on LAYER metal7 = 32 um.
+Total wire length on LAYER metal8 = 0 um.
+Total wire length on LAYER metal9 = 0 um.
+Total wire length on LAYER metal10 = 0 um.
+Total number of vias = 2223.
+Up-via summary (total 2223):.
+
+---------------
+ active       0
+ metal1    1151
+ metal2    1037
+ metal3      22
+ metal4       7
+ metal5       4
+ metal6       2
+ metal7       0
+ metal8       0
+ metal9       0
+---------------
+           2223
+
+
+[INFO DRT-0198] Complete detail routing.
+```
+
+View the resulting detail routing in GUI as follows:
+
+![Detail Routing](./images/sky130_gcd_route.webp)
+
+### Antenna Checker
+
+Antenna Violation occurs when the antenna ratio exceeds a value specified
+in a Process Design Kit (PDK). The antenna ratio is the ratio of the gate
+area to the gate oxide area. The amount of charge collection is determined
+by the area/size of the conductor (gate area).
+
+This tool checks antenna violations and generates a report to indicate violated nets.
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/ant/test/ant_check.tcl).
+
+Launch OpenROAD by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/ant/test/
+openroad
+```
+
+To extract antenna violations, run the following commands:
+
+```tcl
+read_lef ant_check.lef
+read_def ant_check.def
+
+check_antennas -verbose
+puts "violation count = [ant::antenna_violation_count]"
+
+# check if net50 has a violation
+set net "net50"
+puts "Net $net violations: [ant::check_net_violation $net]"
+```
+
+The log as follows:
+
+```
+[INFO ANT-0002] Found 1 net violations.
+[INFO ANT-0001] Found 2 pin violations.
+violation count = 1
+Net net50 violations: 1
+```
+
+### Metal Fill
+
+Metal fill is a mandatory step at advanced nodes to ensure manufacturability
+and high yield. It involves filling the empty or white spaces near the
+design with metal polygons to ensure regular planarization of the wafer.
+
+This module inserts floating metal fill shapes to meet metal density
+design rules while obeying DRC constraints. It is driven by a json
+configuration file.
+
+Command used as follows:
+```tcl
+density_fill -rules <json_file> [-area <list of lx ly ux uy>]
+```
+If -area is not specified, the core area will be used.
+
+To run metal fill post route, run the following:
+```shell
+cd flow/tutorials/scripts/metal_fill
+openroad -gui
+source "helpers.tcl"
+read_db ./5_route.odb
+```
+Layout before adding metal fill is as follows:
+![Detail Routing](./images/sky130_gcd_route.webp)
+
+To add metal fill, run the command:
+```tcl
+density_fill -rules ../../../platforms/sky130hd/fill.json
+```
+
+Layout after adding metal fill insertion is as follows:
+![Metal Fill](./images/metal_fill_view.webp)
+
+Metal fill view can enabled with `Misc` and enable `Fills` check box.
+
+### Parasitics Extraction
+
+OpenRCX is a Parasitic Extraction (PEX, or RCX) tool that works on OpenDB design APIs.
+It extracts routed designs based on the LEF/DEF layout model.
+
+OpenRCX stores resistance, coupling capacitance and ground (i.e., grounded) capacitance
+on OpenDB objects with direct pointers to the associated wire and via db
+objects. Optionally, OpenRCX can generate a `.spef` file.
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/rcx/test/45_gcd.tcl).
+
+Launch OpenROAD tool by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/rcx/test/
+openroad
+```
+
+To run parasitics for gcd design:
+```tcl
+source 45_gcd.tcl
+```
+
+The log as follows:
+```
+[INFO ODB-0222] Reading LEF file: Nangate45/Nangate45.lef
+[INFO ODB-0223]     Created 22 technology layers
+[INFO ODB-0224]     Created 27 technology vias
+[INFO ODB-0225]     Created 135 library cells
+[INFO ODB-0226] Finished LEF file:  Nangate45/Nangate45.lef
+[INFO ODB-0127] Reading DEF file: 45_gcd.def
+[INFO ODB-0128] Design: gcd
+[INFO ODB-0130]     Created 54 pins.
+[INFO ODB-0131]     Created 1820 components and 4618 component-terminals.
+[INFO ODB-0132]     Created 2 special nets and 3640 connections.
+[INFO ODB-0133]     Created 350 nets and 978 connections.
+[INFO ODB-0134] Finished DEF file: 45_gcd.def
+[INFO RCX-0431] Defined process_corner X with ext_model_index 0
+[INFO RCX-0029] Defined extraction corner X
+[INFO RCX-0008] extracting parasitics of gcd ...
+[INFO RCX-0435] Reading extraction model file 45_patterns.rules ...
+[INFO RCX-0436] RC segment generation gcd (max_merge_res 0.0) ...
+[INFO RCX-0040] Final 2656 rc segments
+[INFO RCX-0439] Coupling Cap extraction gcd ...
+[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
+[INFO RCX-0043] 1954 wires to be extracted
+[INFO RCX-0442] 48% completion -- 954 wires have been extracted
+[INFO RCX-0442] 100% completion -- 1954 wires have been extracted
+[INFO RCX-0045] Extract 350 nets, 2972 rsegs, 2972 caps, 2876 ccs
+[INFO RCX-0015] Finished extracting gcd.
+[INFO RCX-0016] Writing SPEF ...
+[INFO RCX-0443] 350 nets finished
+[INFO RCX-0017] Finished writing SPEF ...
+```
+
+`45_gcd.spef` viewed in `results` directory.
+
+## Troubleshooting Problems
+
+This section shows you how to troubleshoot commonly occurring problems
+with the flow or any of the underlying application tools.
+
+### Debugging Problems in Global Routing
+
+The global router has a few useful functionalities to understand
+high congestion issues in the designs.
+
+Congestion heatmap can be used on any design, whether it has
+congestion or not. Viewing congestion explained [here](content:heat:maps).
+If the design has congestion issue, it ends with the error;
+```
+[ERROR GRT-0118] Routing congestion too high.
+```
+
+Refer to the built-in example [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/grt/test/congestion5.tcl).
+
+Launch OpenROAD GUI by running the following command(s) in the terminal in OpenROAD tool root directory:
+
+```shell
+cd ../tools/OpenROAD/src/grt/test/
+openroad -gui
+```
+
+To run the global routing, run the following commands in `Tcl Commands` of
+GUI:
+
+```tcl
+source congestion5.tcl
+```
+
+The design fail with routing congestion error as follows:
+![Routing_Congestion](./images/grt_congestion_error.webp)
+
+In the GUI, you can go under `Heat Maps` and mark the
+`Routing Congestion` checkbox to visualize the congestion map.
+![congestion_heatmap](./images/congestion_heatmap_enable.webp)
+
+#### Dump congestion information to a text file
+
+You can create a text file with the congestion information of the
+GCells for further investigation on the GUI. To do that, add the
+`-congestion_report_file file_name` to the `global_route` command, as shown below:
+```tcl
+global_route -guide_file out.guide -congestion_report_file congest.rpt
+```
+
+#### Visualization of overflowing GCells as markers
+
+With the file created with the command described above, you can see more
+details about the congested GCell, like the total resources, utilization,
+location, etc. You can load the file following these steps:
+
+-   step 1: In the `DRC Viewer` window, click on `Load` and select the
+    file with the congestion report.
+-   step 2: A summary of the GCells with congestion is shown in the
+    `DRC Viewer` window. Also, the markers are added to the GUI.
+![GCell_marker](./images/gcell_marker.webp)
+-   step 3: For details on the routing resources information, use the `Inspector` window.
+![zoom_options](./images/zoom_options.webp)
+
+By Clicking `zoom_to` options, you can enlarge the view as follows:
+![zoomto_gcell](./images/zoomto_gcell.webp)

data/markdown/ORFS_docs/ORFS-getting_involved.md

@@ -0,0 +1,101 @@
+# OpenROAD Getting Involved
+
+Thank you for taking the time to read this document and to contribute.
+The OpenROAD project will not reach all of its objectives without help!
+
+Possible ways to contribute in the scope of OpenROAD Flow:
+
+- Open-source PDK information
+- Open-source Designs
+- Useful scripts
+- Star our project and repos so we can see the number of people
+    who are interested
+
+## Licensing Contributions
+
+As much as possible, all contributions should be licensed using the BSD3
+license. You can propose another license if you must, but contributions
+made with BSD3 fit best with the spirit of OpenROAD's permissive open-source
+philosophy. We do have exceptions in the project, but over time we hope
+that all contributions will be BSD3, or some other permissive license such as MIT
+or Apache2.0.
+
+## Contributing Open Source PDK information and Designs
+
+If you have new design or PDK information to contribute, please add this
+to the repo
+[OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/).
+In the
+[flow directory](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow)
+you will see a directory for
+[designs](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/designs)
+with Makefiles to run them, and one for PDK
+[platforms](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow/platforms)
+used by the designs. If you add a new PDK platform, be sure to add at
+least one design that uses it.
+
+## Contributing Scripts and Code
+
+We follow the [Google C++ style guide](https://google.github.io/styleguide/cppguide.html).
+If you find code in our project that does *not* follow this guide, then within each file that
+you edit, follow the style in that file.
+
+Please pay careful attention to the
+[tool checklist](https://openroad.readthedocs.io/en/latest/contrib/DeveloperGuide.html#tool-checklist) for all code. If you want
+to add or improve functionality in OpenROAD, please start with the
+top-level [app](https://github.com/The-OpenROAD-Project/OpenROAD/) repo. You
+can see in the `src` directory that submodules exist pointing to tested
+versions of the other relevant repos in the project. Please look at the
+tool workflow in the developer guide [document](DeveloperGuide.md)
+to work with the app and its submodule repos in an efficient way.
+
+Please run clang-format on all the C++ source files that you change, before
+committing. In the root directory of the OpenROAD repository there is the
+file `.clang-format` that defines all coding formatting rules.
+
+Please pay attention to the
+[test directory](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/test)
+and be sure to add tests for any code changes that you make, using open-source
+PDK and design information. We provide the `nangate45` PDK in
+the OpenROAD-flow-scripts repo to help with this. Pull requests with
+code changes are unlikely to be accepted without accompanying test
+cases. There are many
+[examples](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/test/gcd_nangate45.tcl)
+tests. Each repo has a test directory as well with tests you should run
+and add to if you modify something in one of the submodules.
+
+For changes that claim to improve QoR or PPA, please run many tests and
+ensure that the improvement is not design-specific. There are designs in
+the
+[OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/)
+repo which can be used unless the improvement is technology-specific.
+
+Do not add runtime or build dependencies without serious thought. For a
+project like OpenROAD with many application subcomponents, the software
+architecture can quickly get out of control. Changes with lots of new
+dependencies which are not necessary are less likely to be integrated.
+
+If you want to add Tcl code to define a new tool command, look at [pdngen](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/pdn)
+as an example of how to do so. Take a look at the
+[CMakeLists file](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/CMakeLists.txt)
+which automatically sources the Tcl code and the
+[Tcl file](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pdn/src/pdn.tcl)
+itself.
+
+To accept contributions, we require each commit to be made with a DCO (Developer
+Certificate of Origin) attached.
+When you commit you add the `-s` flag to your commit. For example:
+
+``` shell
+git commit -s -m "test dco with -s"
+```
+
+This will append a statement to your commit comment that attests to the DCO. GitHub
+has built in the `-s` option to its command line since use of this is so
+pervasive. The promise is very basic, certifying that you know that you
+have the right to commit the code. Please read the  [full statement
+here](https://developercertificate.org/).
+
+## Questions
+
+Please refer to our [FAQs](../user/FAQS.md).

data/markdown/ORFS_docs/ORFS-git_guide.md

@@ -0,0 +1,207 @@
+# Git Quickstart
+
+This tutorial serves as a quickstart to Git and contributing to our repository. If you have not already set up OpenROAD-flow-scripts, please follow the instructions [here](../../index.md#build-or-installing-orfs-dependencies). 
+
+```{tip} This basic tutorial gives instruction for basic password Git authentication.
+If you would like to setup SSH authentication, please follow this [guide](https://help.github.com/set-up-git-redirect).
+```
+
+## Forking
+
+You will need your own fork to work on the code. Go to the `OpenROAD-flow-scripts` project
+[page](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts) and hit the `Fork` button. You will
+want to clone your fork to your machine:
+
+```shell
+git clone https://github.com/your-user-name/OpenROAD-flow-scripts.git
+cd OpenROAD-flow-scripts
+git remote add upstream https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git
+git fetch upstream
+```
+
+This creates the directory `OpenROAD-flow-scripts` and connects your repository to
+the upstream (master project) *OpenROAD-flow-scripts* repository.
+
+## Creating a branch
+
+You want your master branch to reflect only production-ready code, so create a
+feature branch for making your changes. For example:
+
+```shell
+git checkout master && git branch shiny-new-feature
+git checkout shiny-new-feature
+# Or equivalently, 
+git checkout master && checkout -b shiny-new-feature 
+```
+
+This changes your working directory to the shiny-new-feature branch.  Keep any
+changes in this branch specific to one bug or feature so it is clear
+what the branch brings to OpenROAD-flow-scripts. You can have many shiny-new-features
+and switch in between them using the git checkout command.
+
+When creating this branch, make sure your master branch is up to date with
+the latest upstream master version. To update your local master branch, you
+can do:
+
+```shell
+git checkout master
+git pull upstream master
+```
+
+When you want to update the feature branch with changes in master after
+you created the branch, check the section on 
+[updating a PR](#updating-your-pull-request).
+
+## Committing your code
+Keep style fixes to a separate commit to make your pull request more readable. Once you've made changes, you can see them by typing:
+
+```shell
+git status
+```
+
+If you have created a new file, it is not being tracked by git. Add it by typing:
+```shell
+git add path/to/file-to-be-added.py
+```
+
+Doing `git status` again should give something like:
+```shell
+# On branch shiny-new-feature
+#
+#       modified:   /relative/path/to/file-you-added.py
+#
+```
+
+Finally, commit your changes to your local repository with an explanatory commit
+message. Do note the `-s` option is needed for developer signoff. 
+```shell
+git commit -s -m "your commit message goes here"
+```
+
+## Pushing your changes
+
+When you want your changes to appear publicly on your GitHub page, push your
+forked feature branch's commits:
+
+```shell
+git push origin shiny-new-feature
+```
+
+Here `origin` is the default name given to your remote repository on GitHub.
+You can see the remote repositories:
+
+```shell
+git remote -v
+```
+
+If you added the upstream repository as described above you will see something
+like:
+
+```shell
+origin  https://github.com/your-user-name/OpenROAD-flow-scripts.git (fetch)
+origin  https://github.com/your-user-name/OpenROAD-flow-scripts.git (push)
+upstream        https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git (fetch)
+upstream        https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git (push)
+```
+
+Now your code is on GitHub, but it is not yet a part of the OpenROAD-flow-scripts project. For that to
+happen, a pull request needs to be submitted on GitHub.
+
+## Review your code
+
+When you're ready to ask for a code review, file a pull request. Before you do, once
+again make sure that you have followed all the guidelines outlined in the [Developer's Guide](./DeveloperGuide.md)
+regarding code style, tests, performance tests, and documentation. You should also
+double check your branch changes against the branch it was based on:
+
+1. Navigate to your repository on GitHub -- https://github.com/your-user-name/OpenROAD-flow-scripts
+1. Click on `Branches`
+1. Click on the `Compare` button for your feature branch
+1. Select the `base` and `compare` branches, if necessary. This will be `master` and
+   `shiny-new-feature`, respectively.
+
+## Submitting the pull request
+
+If everything looks good, you are ready to make a pull request. A pull request is how
+code from a local repository becomes available to the GitHub community and can be looked
+at and eventually merged into the master version. This pull request and its associated
+changes will eventually be committed to the master branch and available in the next
+release. To submit a pull request:
+
+1. Navigate to your repository on GitHub
+1. Click on the ``Compare & pull request`` button
+1. You can then click on ``Commits`` and ``Files Changed`` to make sure everything looks
+   okay one last time
+1. Write a description of your changes in the ``Preview Discussion`` tab
+1. Click ``Send Pull Request``.
+
+This request then goes to the repository maintainers, and they will review
+the code.
+
+## Updating your pull request
+
+Based on the review you get on your pull request, you will probably need to make
+some changes to the code. In that case, you can make them in your branch,
+add a new commit to that branch, push it to GitHub, and the pull request will be
+automatically updated.  Pushing them to GitHub again is done by:
+
+```shell
+git push origin shiny-new-feature
+```
+
+This will automatically update your pull request with the latest code and restart the
+[Continuous Integration](./CI.md) tests.
+
+Another reason you might need to update your pull request is to solve conflicts
+with changes that have been merged into the master branch since you opened your
+pull request.
+
+To do this, you need to `merge upstream master` in your branch:
+
+```shell
+git checkout shiny-new-feature
+git fetch upstream
+git merge upstream/master
+```
+
+If there are no conflicts (or they could be fixed automatically), a file with a
+default commit message will open, and you can simply save and quit this file.
+
+If there are merge conflicts, you need to solve those conflicts. See 
+this [article](https://help.github.com/articles/resolving-a-merge-conflict-using-the-command-line/)
+for an explanation on how to do this.
+Once the conflicts are merged and the files where the conflicts were solved are
+added, you can run ``git commit`` to save those fixes.
+
+If you have uncommitted changes at the moment you want to update the branch with
+master, you will need to ``stash`` them prior to updating. 
+
+```{seealso}
+See the stash [docs](https://git-scm.com/book/en/v2/Git-Tools-Stashing-and-Cleaning).
+```
+This will effectively store your changes and they can be reapplied after updating.
+
+After the feature branch has been updated locally, you can now update your pull
+request by pushing to the branch on GitHub:
+
+```shell
+git push origin shiny-new-feature
+```
+
+## Tips for a successful pull request
+
+If you have made it to the `Review your code` phase, one of the core contributors may
+take a look. Please note however that a handful of people are responsible for reviewing
+all of the contributions, which can often lead to bottlenecks.
+
+To improve the chances of your pull request being reviewed, you should:
+
+- **Reference an open issue** for non-trivial changes to clarify the PR's purpose
+- **Ensure you have appropriate tests**. These should be the first part of any PR
+- **Keep your pull requests as simple as possible**. Larger PRs take longer to review
+- **Ensure that CI is in a green state**. Reviewers may not even look otherwise
+- **Keep updating your pull request**, either by request or every few days
+
+## Acknowledgements
+
+This page has been adapted from [pandas Developer Guide](https://pandas.pydata.org/docs/development/contributing.html). 

data/markdown/ORFS_docs/ORFS-notebooks.md

@@ -0,0 +1,19 @@
+# Colab Quickstart
+
+Notebook-based packaging offers three main benefits:
+1. Colab is completely free to use and can be accessed from any web browser.
+1. Colab notebooks can be easily shared with others, making it a great 
+   tool for teams to collaborate and manage OpenROAD design runs. 
+1. The notebook can easily be modified to be used for on-premise servers or 
+   notebook-based cloud providers such as LambdaLabs/Paperspace. 
+
+We provide two notebooks for a quickstart to OpenROAD-flow-scripts functionality 
+as follows:
+
+## OpenROAD-flow-scripts Automated RTL-GDSII Flow
+
+The notebook for the automated flow for `gcd` design in `nangate45` technology node can be found [here](https://colab.research.google.com/drive/1bfcvqOnbw8q7FmSONLw8q7-yBVvKsQot).
+
+## AutoTuner Flow
+
+The notebook for the OpenROAD-flow-scripts AutoTuner flow for `gcd` design in `sky130hd` technology node can be found [here](https://colab.research.google.com/drive/1wye0osn34YVWPvTrfBTftjOfGOtF3ABe).

data/markdown/ORFS_docs/ORFS-userguide.md

@@ -0,0 +1,44 @@
+# OpenRoad Flow Scripts User Guide
+
+The OpenROAD Project uses three tools to perform automated RTL-to-GDS layout generation:
+
+1.  [yosys](https://github.com/The-OpenROAD-Project/yosys): Logic
+    Synthesis
+2.  [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD):
+    Floorplanning through Detailed Routing
+3.  [KLayout](https://www.klayout.de/): GDS merge, DRC and LVS (public
+    PDKs)
+
+To automate RTL-to-GDS we provide
+[OpenROAD Flow](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts),
+which contains scripts that integrate the three tools.
+
+## Code Organization
+
+The [OpenROAD Flow](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts)
+repository serves as an example RTL-to-GDS flow using the OpenROAD
+tools. The script `build_openroad.sh` in the repository will
+automatically build the OpenROAD toolchain.
+
+The two main directories are:
+
+1. `tools/`: contains the source code for the entire yosys and
+   [OpenROAD App](https://github.com/The-OpenROAD-Project/OpenROAD)
+   (both via submodules) as well as other tools required for the flow.
+3. `flow/`: contains reference recipes and scripts to run designs
+   through the flow. It also contains public platforms and test
+   designs.
+
+## Setup
+
+See [Getting Started](../index.md#getting-started-with-openroad-flow-scripts) guide.
+
+## Using the OpenROAD Flow
+
+See the documentation [here](../tutorials/FlowTutorial.md) for details about the
+flow and how to run designs through the flow.
+
+## Using the OpenROAD App
+
+See the documentation [here](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/README.md) for details about the app and
+the available features and commands.

data/markdown/OR_docs/OR_getting_involved.md

@@ -0,0 +1,87 @@
+# Getting Involved
+
+Thank you for taking the time to read this document and to contribute.
+The OpenROAD project will not reach all of its objectives without help!
+
+Possible ways to contribute to the OpenROAD application:
+
+- Tool improvements
+- New tools
+- Improvements to documentation, including this document
+- Star our project and repos so we can see the number of people
+    who are interested
+
+## Licensing Contributions
+
+As much as possible, all contributions should be licensed using the BSD3
+license. You can propose another license if you must, but contributions
+made with BSD3 fit best with the spirit of OpenROAD's permissive open-source
+philosophy. We do have exceptions in the project, but over time we hope
+that all contributions will be BSD3, or some other permissive license such as MIT
+or Apache2.0.
+
+## Contributing Scripts and Code
+
+We follow the [Google C++ style guide](https://google.github.io/styleguide/cppguide.html).
+If you find code in our project that does *not* follow this guide, then within each file that
+you edit, follow the style in that file.
+
+Please pay careful attention to the
+[tool checklist](DeveloperGuide.md#tool-checklist) for all code. If you want
+to add or improve functionality in OpenROAD, please start with the
+top-level [app](https://github.com/The-OpenROAD-Project/OpenROAD/) repo. You
+can see in the `src` directory that submodules exist pointing to tested
+versions of the other relevant repos in the project. Please look at the
+tool workflow in the developer guide [document](DeveloperGuide.md)
+to work with the app and its submodule repos in an efficient way.
+
+Please run clang-format on all the C++ source files that you change, before
+committing. In the root directory of the OpenROAD repository there is the
+file `.clang-format` that defines all coding formatting rules.
+
+Please pay attention to the
+[test directory](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/test)
+and be sure to add tests for any code changes that you make, using open-source
+PDK and design information. We provide the `nangate45` PDK in
+the OpenROAD-flow-scripts repo to help with this. Pull requests with
+code changes are unlikely to be accepted without accompanying test
+cases. There are many
+[examples](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/test/gcd_nangate45.tcl)
+tests. Each repo has a test directory as well with tests you should run
+and add to if you modify something in one of the submodules.
+
+For changes that claim to improve QoR or PPA, please run many tests and
+ensure that the improvement is not design-specific. There are designs in
+the
+[OpenROAD-flow-scripts](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/)
+repo which can be used unless the improvement is technology-specific.
+
+Do not add runtime or build dependencies without serious thought. For a
+project like OpenROAD with many application subcomponents, the software
+architecture can quickly get out of control. Changes with lots of new
+dependencies which are not necessary are less likely to be integrated.
+
+If you want to add Tcl code to define a new tool command, look at [pdngen](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/pdn)
+as an example of how to do so. Take a look at the
+[CMake file](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/CMakeLists.txt)
+which automatically sources the Tcl code and the
+[Tcl file](https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/pdn/src/pdn.tcl)
+itself.
+
+To accept contributions, we require each commit to be made with a DCO (Developer
+Certificate of Origin) attached.
+When you commit you add the `-s` flag to your commit. For example:
+
+``` shell
+git commit -s -m "test dco with -s"
+```
+
+This will append a statement to your commit comment that attests to the DCO. GitHub
+has built in the `-s` option to its command line since use of this is so
+pervasive. The promise is very basic, certifying that you know that you
+have the right to commit the code. Please read the  [full statement
+here](https://developercertificate.org/).
+
+## Questions
+
+Please refer to our [FAQs](../user/FAQS.md).

data/markdown/OR_docs/OR_install_instructions.md

@@ -0,0 +1,385 @@
+#!/usr/bin/env bash
+# This script builds the OpenROAD Flow tools locally from source or in a Docker image.
+
+# Exit on first error, do not allow unbound variables
+set -eu
+
+# Make sure we are on the correct folder before beginning
+cd "$(dirname $(readlink -f $0))"
+
+# Set up paths to dependencies, such as cmake and boost. Safe no-op
+# if tools were set up elsewhere in the path.
+. dev_env.sh
+
+# Defaults variable values
+NICE=""
+
+OPENROAD_APP_REMOTE="origin"
+OPENROAD_APP_BRANCH="master"
+
+INSTALL_PATH="$(pwd)/tools/install"
+
+YOSYS_USER_ARGS=""
+YOSYS_ARGS="CONFIG=gcc"
+
+OPENROAD_APP_USER_ARGS=""
+OPENROAD_APP_ARGS=""
+
+LSORACLE_USER_ARGS=""
+LSORACLE_ARGS="\
+-D CMAKE_BUILD_TYPE=RELEASE \
+-D YOSYS_INCLUDE_DIR=$(pwd)/tools/yosys \
+-D YOSYS_PLUGIN=ON \
+"
+
+DOCKER_OS_NAME="ubuntu22.04"
+PROC=-1
+
+function usage() {
+        cat << EOF
+
+Usage: $0 [-h|--help] [-o|--local] [-l|--latest]
+          [--or_branch BRANCH_NAME] [--or_repo REPO_URL] [--no_init]
+          [-n|--nice] [-t|--threads N]
+          [--yosys-args-overwrite] [--yosys-args STRING]
+          [--openroad-args-overwrite] [--openroad-args STRING]
+          [--lsoracle-args-overwrite] [--lsoracle-args STRING]
+          [--install-path PATH] [--clean] [--clean-force]
+
+          [-c|--copy-platforms]
+
+Options:
+    -h, --help              Print this help message.
+
+    -o, --local             Build locally instead of building a Docker image.
+
+    -l, --latest            Use the head of branch --or_branch or 'master'
+                            by default for tools/OpenROAD.
+
+    --or_branch BRANCH_NAME Use the head of branch BRANCH for tools/OpenROAD.
+
+    --or_repo REPO_URL      Use a fork at REPO-URL (https/ssh) for tools/OpenROAD.
+
+    --no_init               Skip initializing submodules.
+
+    -t, --threads N         Use N cpus when compiling software.
+
+    -n, --nice              Nice all jobs. Use all cpus unless --threads is
+                            also given, then use N threads.
+
+    --yosys-args-overwrite  Do not use default flags set by this scrip during
+                            Yosys compilation.
+
+    --yosys-args STRING      Aditional compilation flags for Yosys compilation.
+
+    --openroad-args-overwrite
+                            Do not use default flags set by this scrip during
+                            OpenROAD app compilation.
+
+    --openroad-args STRING  Aditional compilation flags for OpenROAD app
+                            compilation.
+
+    --lsoracle-enable       Compile LSOracle. Disable by default as it is not
+                            currently used on the flow.
+
+    --lsoracle-args-overwrite
+                            Do not use default flags set by this script during
+                            LSOracle compilation.
+
+    --lsoracle-args STRING    Aditional compilation flags for LSOracle
+                            compilation.
+
+    --install-path PATH     Path to install tools. Default is ${INSTALL_PATH}.
+
+    --clean                 Call git clean interactively before compile.
+                            Useful to remove old build files.
+
+    --clean-force           Call git clean before compile. WARNING: this option
+                            will not ask for confirmation. Useful to remove
+                            old build files.
+
+
+Options valid only for Docker builds:
+    -c, --copy-platforms    Copy platforms to inside docker image.
+
+    --os=DOCKER_OS_NAME     Choose beween ubuntu22.04 (default), ubuntu20.04.
+
+    This script builds the OpenROAD tools: openroad, yosys and yosys plugins.
+    By default, the tools will be built from the linked submodule hashes.
+
+EOF
+}
+
+# Parse arguments
+__CMD="$0 $@"
+while (( "$#" )); do
+        case "$1" in
+                -h|--help)
+                        usage 2> /dev/null
+                        exit
+                        ;;
+                -o|--local)
+                        LOCAL_BUILD=1
+                        ;;
+                -l|--latest)
+                        USE_OPENROAD_APP_LATEST=1
+                        ;;
+                --or_branch)
+                        OPENROAD_APP_BRANCH="$2"
+                        shift
+                        ;;
+                --or_repo)
+                        OPENROAD_APP_GIT_URL="$2"
+                        shift
+                        ;;
+                --no_init)
+                        OPENROAD_FLOW_NO_GIT_INIT=1
+                        ;;
+                -t|--threads)
+                        PROC="$2"
+                        shift
+                        ;;
+                -n|--nice)
+                        NICE="nice"
+                        ;;
+                -c|--copy-platforms)
+                        DOCKER_COPY_PLATFORMS=1
+                        ;;
+                --yosys-args-overwrite)
+                        YOSYS_OVERWIRTE_ARGS=1
+                        ;;
+                --yosys-args)
+                        YOSYS_USER_ARGS="$2"
+                        shift
+                        ;;
+                --openroad-args-overwrite)
+                        OPENROAD_APP_OVERWIRTE_ARGS=1
+                        ;;
+                --openroad-args)
+                        OPENROAD_APP_USER_ARGS="$2"
+                        shift
+                        ;;
+                --lsoracle-enable)
+                        LSORACLE_ENABLE=1
+                        ;;
+                --lsoracle-args-overwrite)
+                        LSORACLE_OVERWIRTE_ARGS=1
+                        ;;
+                --lsoracle-args)
+                        LSORACLE_USER_ARGS="$2"
+                        shift
+                        ;;
+                --install-path)
+                        INSTALL_PATH="$2"
+                        shift
+                        ;;
+                --clean)
+                        CLEAN_BEFORE=1
+                        ;;
+                --clean-force)
+                        CLEAN_BEFORE=1
+                        CLEAN_FORCE=1
+                        ;;
+                --os=* )
+                        DOCKER_OS_NAME="${1#*=}"
+                        ;;
+                -*|--*) # unsupported flags
+                        echo "[ERROR FLW-0005] Unsupported flag $1." >&2
+                        usage 2> /dev/null
+                        exit 1
+                        ;;
+        esac
+        shift
+done
+
+if [[ "$PROC" == "-1" ]]; then
+        if [[ "$OSTYPE" == "linux-gnu"* ]]; then
+                PROC=$(nproc --all)
+        elif [[ "$OSTYPE" == "darwin"* ]]; then
+                PROC=$(sysctl -n hw.ncpu)
+        else
+                cat << EOF
+[WARNING FLW-0025] Unsupported OSTYPE: cannot determine number of host CPUs"
+  Defaulting to 2 threads. Use --threads N to use N threads"
+EOF
+  PROC=2
+        fi
+fi
+
+# Only add install prefix variables after parsing arguments.
+YOSYS_ARGS+=" PREFIX=${INSTALL_PATH}/yosys"
+OPENROAD_APP_ARGS+=" -D CMAKE_INSTALL_PREFIX=${INSTALL_PATH}/OpenROAD"
+if [ -n "$CMAKE_INSTALL_RPATH" ]; then
+        OPENROAD_APP_ARGS+=" -D CMAKE_INSTALL_RPATH=${CMAKE_INSTALL_RPATH}"
+        OPENROAD_APP_ARGS+=" -D CMAKE_INSTALL_RPATH_USE_LINK_PATH=TRUE"
+fi
+LSORACLE_ARGS+=" \
+-D YOSYS_SHARE_DIR=${INSTALL_PATH}/yosys/share/yosys \
+-D CMAKE_INSTALL_PREFIX=${INSTALL_PATH}/LSOracle \
+"
+
+__args_setup() {
+        if [ ! -z "${YOSYS_OVERWIRTE_ARGS+x}" ]; then
+                echo "[INFO FLW-0014] Overwriting Yosys compilation flags."
+                YOSYS_ARGS="${YOSYS_USER_ARGS}"
+        else
+                YOSYS_ARGS+=" ${YOSYS_USER_ARGS}"
+        fi
+
+        if [ ! -z "${OPENROAD_APP_OVERWIRTE_ARGS+x}" ]; then
+                echo "[INFO FLW-0015] Overwriting OpenROAD app compilation flags."
+                OPENROAD_APP_ARGS="${OPENROAD_APP_USER_ARGS}"
+        else
+                OPENROAD_APP_ARGS+=" ${OPENROAD_APP_USER_ARGS}"
+        fi
+
+        if [ ! -z "${LSORACLE_OVERWIRTE_ARGS+x}" ]; then
+                echo "[INFO FLW-0016] Overwriting LSOracle compilation flags."
+                LSORACLE_ARGS="${LSORACLE_USER_ARGS}"
+        else
+                LSORACLE_ARGS+=" ${LSORACLE_USER_ARGS}"
+        fi
+}
+
+__docker_build()
+{
+        echo "[INFO FLW-0020] Building docker image for OpenROAD Flow."
+        if [ ! -z "${DOCKER_COPY_PLATFORMS+x}" ]; then
+                cp .dockerignore{,.bak}
+                sed -i '/flow\/platforms/d' .dockerignore
+        fi
+        ./etc/DockerHelper.sh create -target=dev -os="${DOCKER_OS_NAME}" -threads="${PROC}"
+        ./etc/DockerHelper.sh create -target=builder -os="${DOCKER_OS_NAME}" -threads="${PROC}"
+        if [ ! -z "${DOCKER_COPY_PLATFORMS+x}" ]; then
+                mv .dockerignore{.bak,}
+        fi
+}
+
+__local_build()
+{
+        if [[ "$OSTYPE" == "darwin"* ]]; then
+          export PATH="$(brew --prefix bison)/bin:$(brew --prefix flex)/bin:$(brew --prefix tcl-tk)/bin:$PATH"
+          export CMAKE_PREFIX_PATH=$(brew --prefix or-tools)
+        fi
+        if [[ -f "/opt/rh/rh-python38/enable" ]]; then
+            set +u
+            source /opt/rh/rh-python38/enable
+            set -u
+        fi
+        if [[ -f "/opt/rh/devtoolset-8/enable" ]]; then
+            # the scl script has unbound variables
+            set +u
+            source /opt/rh/devtoolset-8/enable
+            set -u
+        fi
+
+        echo "[INFO FLW-0017] Compiling Yosys."
+        ${NICE} make install -C tools/yosys -j "${PROC}" ${YOSYS_ARGS}
+
+        echo "[INFO FLW-0018] Compiling OpenROAD."
+        eval ${NICE} cmake tools/OpenROAD -B tools/OpenROAD/build ${OPENROAD_APP_ARGS}
+        ${NICE} cmake --build tools/OpenROAD/build --target install -j "${PROC}"
+
+        if [ ! -z "${LSORACLE_ENABLE+x}" ]; then
+                echo "[INFO FLW-0019] Compiling LSOracle."
+                ${NICE} cmake tools/LSOracle -B tools/LSOracle/build ${LSORACLE_ARGS}
+                ${NICE} cmake --build tools/LSOracle/build --target install -j "${PROC}"
+        fi
+}
+
+__update_openroad_app_remote()
+(
+        cd tools/OpenROAD
+        remotes=$(git remote)
+        SAVEIFS=$IFS
+        IFS=$'\n'
+        remotes=($remotes)
+        IFS=$SAVEIFS
+        if [[ ! " ${remotes[@]} " =~ " ${OPENROAD_APP_REMOTE} " ]]; then
+                git remote add "${OPENROAD_APP_REMOTE}" "${OPENROAD_APP_GIT_URL}"
+        fi
+)
+
+__change_openroad_app_remote()
+{
+        base_url=$(dirname "${OPENROAD_APP_GIT_URL}")
+        if [[ ${base_url##*/} = $base_url ]]; then
+                OPENROAD_APP_REMOTE=${base_url##*:}
+        else
+                OPENROAD_APP_REMOTE=${base_url##*/}
+        fi
+        __update_openroad_app_remote
+}
+
+__update_openroad_app_latest()
+(
+        cd tools/OpenROAD
+        git fetch "${OPENROAD_APP_REMOTE}"
+        git checkout "${OPENROAD_APP_REMOTE}/${OPENROAD_APP_BRANCH}"
+        git pull "${OPENROAD_APP_REMOTE}" "${OPENROAD_APP_BRANCH}"
+        git submodule update --init --recursive
+)
+
+__common_setup()
+{
+        # Clone repositories
+        if [ -z "${OPENROAD_FLOW_NO_GIT_INIT+x}" ]; then
+                echo "[INFO FLW-0002] Updating git submodules."
+                git submodule update --init --recursive
+        fi
+
+        if [ ! -z "${OPENROAD_APP_GIT_URL+x}" ]; then
+                echo -n "[INFO FLW-0003] Changing OpenROAD app remote to"
+                echo " ${OPENROAD_APP_GIT_URL}."
+                __change_openroad_app_remote
+        fi
+
+        if [ ! -z "${USE_OPENROAD_APP_LATEST+x}" ] || [ "${OPENROAD_APP_BRANCH}" != "master" ]; then
+                echo -n "[INFO FLW-0004] Updating OpenROAD app to the HEAD"
+                echo "  of ${OPENROAD_APP_REMOTE}/${OPENROAD_APP_BRANCH}."
+                __update_openroad_app_latest
+        fi
+}
+
+__logging()
+{
+        local log_file="build_openroad.log"
+        echo "[INFO FLW-0027] Saving logs to ${log_file}"
+        echo "[INFO FLW-0028] $__CMD"
+        exec > >(tee -i "${log_file}")
+        exec 2>&1
+}
+
+__cleanup()
+{
+        if [ ! -z "${CLEAN_FORCE+x}" ]; then
+                CLEAN_CMD="-x -d --force"
+        else
+                CLEAN_CMD="-x -d --interactive"
+        fi
+        echo "[INFO FLW-0026] Cleaning up previous binaries and build files."
+        git clean ${CLEAN_CMD} tools
+        YOSYS_ABC_PATH="tools/yosys/abc"
+        if [[ -d "${YOSYS_ABC_PATH}" ]]; then
+                echo "Entering '${YOSYS_ABC_PATH}'"
+                git --work-tree=${YOSYS_ABC_PATH} --git-dir=${YOSYS_ABC_PATH}/.git clean ${CLEAN_CMD}
+        fi
+        git submodule foreach --recursive git clean ${CLEAN_CMD}
+}
+
+__logging
+if [ ! -z "${CLEAN_BEFORE+x}" ]; then
+        __cleanup
+fi
+__args_setup
+__common_setup
+
+# Choose install method
+if [ -z "${LOCAL_BUILD+x}" ] && command -v docker &> /dev/null; then
+        echo -n "[INFO FLW-0000] Using docker build method."
+        __docker_build
+else
+        echo -n "[INFO FLW-0001] Using local build method."
+        echo " This will create binaries at 'tools/install' unless overwritten."
+        __local_build
+fi

data/markdown/OR_docs/OR_readme.md

@@ -0,0 +1,80 @@
+# Welcome to OpenROAD's documentation!
+
+The OpenROAD ("Foundations and Realization of Open, Accessible Design")
+project was launched in June 2018 within the DARPA IDEA program. OpenROAD
+aims to bring down the barriers of cost, expertise and unpredictability that
+currently block designers' access to hardware implementation in advanced
+technologies. The project team (Qualcomm, Arm and multiple universities and
+partners, led by UC San Diego) is developing a fully autonomous, open-source
+tool chain for digital SoC layout generation, focusing on
+the RTL-to-GDSII phase of system-on-chip design. Thus,
+OpenROAD holistically attacks the multiple facets of today's design cost
+crisis: engineering resources, design tool licenses, project schedule,
+and risk.
+
+The IDEA program targets no-human-in-loop (NHIL) design, with 24-hour
+turnaround time and zero loss of power-performance-area (PPA) design quality.
+
+The NHIL target requires tools to adapt and auto-tune successfully to flow
+completion, without (or, with minimal) human intervention. Machine
+intelligence augments human expertise through efficient modeling and
+prediction of flow and optimization outcomes throughout the synthesis, placement
+and routing process. This is complemented by development of metrics
+and machine learning infrastructure.
+
+The 24-hour runtime target implies that problems must be strategically
+decomposed throughout the design process, with clustered and partitioned
+subproblems being solved and recomposed through intelligent distribution
+and management of computational resources. This ensures that the NHIL design
+optimization is performed within its available `[threads * hours]` "box" of
+resources. Decomposition that enables parallel and distributed search over
+cloud resources incurs a quality-of-results loss, but this is subsequently
+recovered through improved flow predictability and enhanced optimization.
+
+For a technical description of the OpenROAD flow, please refer to our DAC-2019 paper:
+[Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project](https://vlsicad.ucsd.edu/Publications/Conferences/371/c371.pdf).
+The paper is also available from [ACM Digital Library](https://dl.acm.org/doi/10.1145/3316781.3326334).
+Other publications and presentations are
+linked [here](https://theopenroadproject.org/publications/).
+
+## Documentation
+
+The OpenROAD Project has two releases:
+
+- Application ([github](https://github.com/The-OpenROAD-Project/OpenROAD)) ([docs](main/README.md)): The application is a standalone binary for digital place and route that can be used by any other RTL-GDSII flow controller.
+- Flow ([github](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts)) ([docs](https://openroad-flow-scripts.readthedocs.io/en/latest/)): This is the native OpenROAD flow that consists of a set of integrated scripts for an autonomous RTL-GDSII flow using OpenROAD and other open-source tools.
+
+## Code of conduct
+
+Please read our code of conduct [here](main/CODE_OF_CONDUCT.md).
+
+## How to contribute
+
+If you are willing to **contribute**, see the
+[Getting Involved](contrib/GettingInvolved.md) section.
+
+If you are a **developer** with EDA background, learn more about how you
+can use OpenROAD as the infrastructure for your tools in the
+[Developer Guide](contrib/DeveloperGuide.md) section.
+
+OpenROAD uses Git for version control and contributions. 
+Get familiarised with a quickstart tutorial to contribution [here](contrib/GitGuide.md).
+
+## How to get in touch
+
+We maintain the following channels for communication:
+
+-   Project homepage and news: <https://theopenroadproject.org>
+-   Twitter: <https://twitter.com/OpenROAD_EDA>
+-   Issues and bugs:
+    -   OpenROAD: <https://github.com/The-OpenROAD-Project/OpenROAD/issues>
+-   Discussions:
+    -   OpenROAD: <https://github.com/The-OpenROAD-Project/OpenROAD/discussions>
+-   Inquiries: openroad@ucsd.edu
+
+See also our [FAQs](user/FAQS.md).
+
+## Site Map
+
+```{tableofcontents}
+```

data/markdown/OR_docs/OR_userguide.md

@@ -0,0 +1,193 @@
+# OpenROAD User Guide
+
+OpenROAD is run using Tcl scripts. The following commands are used to read
+and write design data.
+
+``` shell
+read_lef [-tech] [-library] filename
+read_def filename
+write_def [-version 5.8|5.7|5.6|5.5|5.4|5.3] filename
+read_verilog filename
+write_verilog filename
+read_db filename
+write_db filename
+write_abstract_lef filename
+```
+
+Use the Tcl `source` command to read commands from a file.
+
+``` shell
+source [-echo] file
+```
+
+If an error is encountered in a command while reading the command file,
+then the error is printed and no more commands are read from the file. If
+`file_continue_on_error` is `1` then OpenROAD will continue reading commands
+after the error.
+
+If `exit_on_error` is `1` then OpenROAD will exit when it encounters an error.
+
+OpenROAD can be used to make a OpenDB database from LEF/DEF, or Verilog
+(flat or hierarchical). Once the database is made it can be saved as a file
+with the `write_db` command. OpenROAD can then read the database with the
+`read_db` command without reading LEF/DEF or Verilog.
+
+The `read_lef` and `read_def` commands can be used to build an OpenDB database
+as shown below. The `read_lef -tech` flag reads the technology portion of a
+LEF file.  The `read_lef -library` flag reads the MACROs in the LEF file.
+If neither of the `-tech` and `-library` flags are specified they default
+to `-tech -library` if no technology has been read and `-library` if a
+technology exists in the database.
+
+``` shell
+read_lef liberty1.lef
+read_def reg1.def
+# Write the db for future runs.
+write_db reg1.db
+```
+
+The `read_verilog` command is used to build an OpenDB database as shown
+below. Multiple Verilog files for a hierarchical design can be read.
+The `link_design` command is used to flatten the design and make a database.
+
+``` shell
+read_lef liberty1.lef
+read_verilog reg1.v
+link_design top
+# Write the db for future runs.
+write_db reg1.db
+```
+
+## Example scripts
+
+Example scripts demonstrating how to run OpenROAD on sample designs can
+be found in /test. Flow tests taking sample designs from synthesizable RTL Verilog
+to detail-routed final layout in the open-source technologies Nangate45 and Sky130HD are
+shown below.
+
+``` shell
+gcd_nangate45.tcl
+aes_nangate45.tcl
+tinyRocket_nangate45.tcl
+gcd_sky130hd.tcl
+aes_sky130hd.tcl
+ibex_sky130hd.tcl
+```
+
+Each of these designs use the common script `flow.tcl`.
+
+## Abstract LEF Support
+
+OpenROAD contains an abstract LEF writer that can take your current design
+and emit an abstract LEF representing the external pins of your design and
+metal obstructions.
+
+
+``` tcl
+write_abstract_lef (-bloat_factor bloat_factor|-bloat_occupied_layers) \
+		   filename
+```
+### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-bloat_factor` | Specifies the bloat factor used when bloating then merging shapes into LEF obstructions. The factor is measured in # of default metal pitches for the respective layer. A factor of `0` will result in detailed LEF obstructions |
+| `-bloat_occupied_layers` | Generates cover obstructions (obstructions over the entire layer) for each layer where shapes are present |
+
+### Examples
+```
+read reg1.db
+
+# Bloat metal shapes by 3 pitches (respectively for every layer) and then merge
+write_abstract_lef -bloat_factor 3 reg1_abstract.lef
+
+# Produce cover obstructions for each layer with shapes present
+write_abstract_lef -bloat_occupied_layers reg1_abstract.lef
+```
+
+### Global Connections
+
+#### Add global connections
+
+The `add_global_connection` command is used to specify how to connect power and ground pins on design instances to the appropriate supplies.
+
+```
+add_global_connection -net net_name \
+                      [-inst_pattern inst_regular_expression] \
+                      -pin_pattern pin_regular_expression \
+                      (-power|-ground) \
+                      [-region region_name]
+```
+
+##### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-net` | Specifies the name of the net in the design to which connections are to be added |
+| `-inst_pattern` | Optional specifies a regular expression to select a set of instances from the design. (Default: .\*) |
+| `-pin_pattern` | Species a regular expression to select pins on the selected instances to connect to the specified net |
+| `-power` | Specifies that the net it a power net |
+| `-ground` | Specifies that the net is a ground net |
+| `-region` | Specifies the name of the region for this rule |
+
+##### Examples
+```
+# Stdcell power/ground pins
+add_global_connection -net VDD -pin_pattern {^VDD$} -power
+add_global_connection -net VSS -pin_pattern {^VSS$} -ground
+
+# SRAM power ground pins
+add_global_connection -net VDD -pin_pattern {^VDDPE$}
+add_global_connection -net VDD -pin_pattern {^VDDCE$}
+add_global_connection -net VSS -pin_pattern {^VSSE$}
+```
+
+#### Perform global connections
+
+The `global_connect` command is used to connect power and ground pins on design instances to the appropriate supplies.
+
+```
+global_connect
+```
+
+#### Clear global connection rules
+
+The `clear_global_connect` command is used remove all defined global connection rules.
+
+```
+clear_global_connect
+```
+
+#### Report global connection rules
+
+The `report_global_connect` command is used print out the currently defined global connection rules.
+
+```
+report_global_connect
+```
+
+#### Report cell type usage
+
+The `report_cell_usage` command is used to print out the usage of cells for each type of cell.
+
+```
+report_cell_usage
+```
+
+## TCL functions
+
+Get the die and core areas as a list in microns: `llx lly urx ury`
+
+```
+ord::get_die_area
+ord::get_core_area
+```
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+openroad+in%3Atitle)
+about this tool.
+
+## License
+
+BSD 3-Clause License.

data/markdown/OR_userguide/OR_README.md

@@ -0,0 +1,193 @@
+# OpenROAD
+
+OpenROAD is run using Tcl scripts. The following commands are used to read
+and write design data.
+
+``` shell
+read_lef [-tech] [-library] filename
+read_def filename
+write_def [-version 5.8|5.7|5.6|5.5|5.4|5.3] filename
+read_verilog filename
+write_verilog filename
+read_db filename
+write_db filename
+write_abstract_lef filename
+```
+
+Use the Tcl `source` command to read commands from a file.
+
+``` shell
+source [-echo] file
+```
+
+If an error is encountered in a command while reading the command file,
+then the error is printed and no more commands are read from the file. If
+`file_continue_on_error` is `1` then OpenROAD will continue reading commands
+after the error.
+
+If `exit_on_error` is `1` then OpenROAD will exit when it encounters an error.
+
+OpenROAD can be used to make a OpenDB database from LEF/DEF, or Verilog
+(flat or hierarchical). Once the database is made it can be saved as a file
+with the `write_db` command. OpenROAD can then read the database with the
+`read_db` command without reading LEF/DEF or Verilog.
+
+The `read_lef` and `read_def` commands can be used to build an OpenDB database
+as shown below. The `read_lef -tech` flag reads the technology portion of a
+LEF file.  The `read_lef -library` flag reads the MACROs in the LEF file.
+If neither of the `-tech` and `-library` flags are specified they default
+to `-tech -library` if no technology has been read and `-library` if a
+technology exists in the database.
+
+``` shell
+read_lef liberty1.lef
+read_def reg1.def
+# Write the db for future runs.
+write_db reg1.db
+```
+
+The `read_verilog` command is used to build an OpenDB database as shown
+below. Multiple Verilog files for a hierarchical design can be read.
+The `link_design` command is used to flatten the design and make a database.
+
+``` shell
+read_lef liberty1.lef
+read_verilog reg1.v
+link_design top
+# Write the db for future runs.
+write_db reg1.db
+```
+
+## Example scripts
+
+Example scripts demonstrating how to run OpenROAD on sample designs can
+be found in /test. Flow tests taking sample designs from synthesizable RTL Verilog
+to detail-routed final layout in the open-source technologies Nangate45 and Sky130HD are
+shown below.
+
+``` shell
+gcd_nangate45.tcl
+aes_nangate45.tcl
+tinyRocket_nangate45.tcl
+gcd_sky130hd.tcl
+aes_sky130hd.tcl
+ibex_sky130hd.tcl
+```
+
+Each of these designs use the common script `flow.tcl`.
+
+## Abstract LEF Support
+
+OpenROAD contains an abstract LEF writer that can take your current design
+and emit an abstract LEF representing the external pins of your design and
+metal obstructions.
+
+
+``` tcl
+write_abstract_lef (-bloat_factor bloat_factor|-bloat_occupied_layers) \
+		   filename
+```
+### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-bloat_factor` | Specifies the bloat factor used when bloating then merging shapes into LEF obstructions. The factor is measured in # of default metal pitches for the respective layer. A factor of `0` will result in detailed LEF obstructions |
+| `-bloat_occupied_layers` | Generates cover obstructions (obstructions over the entire layer) for each layer where shapes are present |
+
+### Examples
+```
+read reg1.db
+
+# Bloat metal shapes by 3 pitches (respectively for every layer) and then merge
+write_abstract_lef -bloat_factor 3 reg1_abstract.lef
+
+# Produce cover obstructions for each layer with shapes present
+write_abstract_lef -bloat_occupied_layers reg1_abstract.lef
+```
+
+### Global Connections
+
+#### Add global connections
+
+The `add_global_connection` command is used to specify how to connect power and ground pins on design instances to the appropriate supplies.
+
+```
+add_global_connection -net net_name \
+                      [-inst_pattern inst_regular_expression] \
+                      -pin_pattern pin_regular_expression \
+                      (-power|-ground) \
+                      [-region region_name]
+```
+
+##### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-net` | Specifies the name of the net in the design to which connections are to be added |
+| `-inst_pattern` | Optional specifies a regular expression to select a set of instances from the design. (Default: .\*) |
+| `-pin_pattern` | Species a regular expression to select pins on the selected instances to connect to the specified net |
+| `-power` | Specifies that the net it a power net |
+| `-ground` | Specifies that the net is a ground net |
+| `-region` | Specifies the name of the region for this rule |
+
+##### Examples
+```
+# Stdcell power/ground pins
+add_global_connection -net VDD -pin_pattern {^VDD$} -power
+add_global_connection -net VSS -pin_pattern {^VSS$} -ground
+
+# SRAM power ground pins
+add_global_connection -net VDD -pin_pattern {^VDDPE$}
+add_global_connection -net VDD -pin_pattern {^VDDCE$}
+add_global_connection -net VSS -pin_pattern {^VSSE$}
+```
+
+#### Perform global connections
+
+The `global_connect` command is used to connect power and ground pins on design instances to the appropriate supplies.
+
+```
+global_connect
+```
+
+#### Clear global connection rules
+
+The `clear_global_connect` command is used remove all defined global connection rules.
+
+```
+clear_global_connect
+```
+
+#### Report global connection rules
+
+The `report_global_connect` command is used print out the currently defined global connection rules.
+
+```
+report_global_connect
+```
+
+#### Report cell type usage
+
+The `report_cell_usage` command is used to print out the usage of cells for each type of cell.
+
+```
+report_cell_usage
+```
+
+## TCL functions
+
+Get the die and core areas as a list in microns: `llx lly urx ury`
+
+```
+ord::get_die_area
+ord::get_core_area
+```
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+openroad+in%3Atitle)
+about this tool.
+
+## License
+
+BSD 3-Clause License.

data/markdown/OR_userguide/OR_ant_README.md

@@ -0,0 +1,78 @@
+# Antenna Rule Checker
+
+This tool checks antenna violations and generates a report to indicate
+violated nets. See LEF/DEF 5.8 Language Reference, Appendix C,
+"Calculating and Fixing Process Antenna Violations" (p.389) 
+for a [description](https://coriolis.lip6.fr/doc/lefdef/lefdefref/lefdefref.pdf) of antenna violations.
+
+This is an example of the detailed and simple reports of the antenna checker:
+
+| <img src="./doc/images/ant_report_print.png" width=500px> |
+
+Abbreviations Index:
+
+-   `PAR`: Partial Area Ratio
+-   `CAR`: Cumulative Area Ratio
+-   `Area`: Gate Area
+-   `S. Area`: Side Diffusion Area
+-   `C. Area`: Cumulative Gate Area
+-   `C. S. Area`: Cumulative Side (Diffusion) Area
+
+Antenna violations can be repaired after global routing with the `repair_design` command.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Check Antennas
+
+```tcl
+check_antennas 
+    [-net net] 
+    [-verbose]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-verbose` | Report all antenna calculations for violating nets. |
+| `-net` | Check antennas on the specified net. |
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+antenna+in%3Atitle)
+about this tool.
+
+## Algorithm
+
+| <img src="./doc/images/example_ant.png" width=400px> | <img src="./doc/images/step1.png" width=400px> |
+|:--:|:--:|
+| Antenna Checker Algorithm: WireGraph Example | Step 1: (a) Start from the root node (ITerm) using upper Via to find a node for a new wire. (b) Save the ITerm area for cumulative gate/diffusion area. |
+| <img src="./doc/images/step2.png" width=400px> | <img src="./doc/images/step3.png" width=400px> |
+| Step 2: From the node of the wire, find all the nodes in the wire through segment wires and find the "root" node of this wire. | Step 3: (a) From the "root" node of the wire, along the outgoing segment edge that goes to other nodes belonging to this wire, calculate the area of this wire. (b) Then, find all the ITerms below these nodes, except for the root node (directly use an ITerm or lower Vias to find ITerms for lower metals). (c) Sum up the areas of all the ITerms found with the cumulative areas and calculate the PAR of this wire. (d) Add the PAR value and the wire info (layer, Index) into the PAR table. Add the new area to the cumulative areas. |
+| <img src="./doc/images/step4.png" width=400px> | <img src="./doc/images/step5.png" width=400px> |
+| Step 4: Find all the upper Vias on this wire (for all the nodes on this wire), and go to the higher-level metal. | Step 5: Repeat Steps 2 and 3 for new-found upper-level wires. |
+| <img src="./doc/images/step6.png" width=400px> | <img src="./doc/images/step7.png" width=400px> |
+| Step 6: Repeat Steps 4 and 5 until we reach a wire that cannot have upper Vias for its nodes (highest-level metal). | Step 7: Pick up another ITerm as a root node and repeat Steps 1 to 6, skipping the wires already in the PAR table. Repeat this for all the ITerms to get a whole PAR table. |
+| <img src="./doc/images/step8.png" width=400px> |
+| Step 8: (a) Pick up a gate ITerm and a node of a wire (e.g., M4,1). Find possible paths that connect them, look up the PAR value of the wires along these paths, and add them up to get the CAR of the (gate, wire) pair. (b) Compare to the AntennaRule to see if the CAR violates the rules. (c) Check this for all (gate, wire) pairs. |
+
+## License
+
+BSD 3-Clause License. See [LICENSE](../../LICENSE) file.

data/markdown/OR_userguide/OR_cts_README.md

@@ -0,0 +1,162 @@
+# Clock Tree Synthesis
+
+The clock tree synthesis module in OpenROAD (`cts`) is based on TritonCTS
+2.0. It is available from the `clock_tree_synthesis` command. TritonCTS 2.0
+performs on-the-fly characterization. Thus, there is no need to generate
+characterization data. The on-the-fly characterization feature can be optionally
+controlled by parameters specified by the `configure_cts_characterization`
+command. Use `set_wire_rc` command to set the clock routing layer.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Configure CTS Characterization
+
+```tcl
+configure_cts_characterization 
+    [-max_slew max_slew]
+    [-max_cap max_cap]
+    [-slew_steps slew_steps]
+    [-cap_steps cap_steps]
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-max_slew` | Max slew value (in the current time unit) that the characterization will test. If this parameter is omitted, the code would use max slew value for specified buffer in `buf_list` from liberty file. |
+| `-max_cap` | Max capacitance value (in the current capacitance unit) that the characterization will test. If this parameter is omitted, the code would use max cap value for specified buffer in `buf_list` from liberty file. |
+| `-slew_steps` | Number of steps that `max_slew` will be divided into for characterization. The default value is `12`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-cap_steps` | Number of steps that `max_cap` will be divided into for characterization. The default value is `34`, and the allowed values are integers `[0, MAX_INT]`. |
+
+### Clock Tree Synthesis
+
+```tcl
+clock_tree_synthesis 
+    -buf_list <list_of_buffers>
+    [-root_buf root_buf]
+    [-wire_unit wire_unit]
+    [-clk_nets <list_of_clk_nets>]
+    [-distance_between_buffers]
+    [-branching_point_buffers_distance]
+    [-clustering_exponent]
+    [-clustering_unbalance_ratio]
+    [-sink_clustering_enable]
+    [-sink_clustering_size cluster_size]
+    [-sink_clustering_max_diameter max_diameter]
+    [-balance_levels]
+    [-num_static_layers]
+    [-sink_clustering_buffer]
+    [-use_dummy_load]
+    [-insertion_delay]
+    [-sink_buffer_max_cap_derate derate_value]
+    [-delay_buffer_derate derate_value]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-buf_list` | Tcl list of master cells (buffers) that will be considered when making the wire segments (e.g. `{BUFXX, BUFYY}`). |
+| `-root_buffer` | The master cell of the buffer that serves as root for the clock tree. If this parameter is omitted, the first master cell from `-buf_list` is taken. |
+| `-wire_unit` | Minimum unit distance between buffers for a specific wire. If this parameter is omitted, the code gets the value from ten times the height of `-root_buffer`. |
+| `-clk_nets` | String containing the names of the clock roots. If this parameter is omitted, `cts` automatically looks for the clock roots automatically. |
+| `-distance_between_buffers` | Distance (in microns) between buffers that `cts` should use when creating the tree. When using this parameter, the clock tree algorithm is simplified and only uses a fraction of the segments from the LUT. |
+| `-branching_point_buffers_distance` | Distance (in microns) that a branch has to have in order for a buffer to be inserted on a branch end-point. This requires the `-distance_between_buffers` value to be set. |
+| `-clustering_exponent` | Value that determines the power used on the difference between sink and means on the CKMeans clustering algorithm. The default value is `4`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-clustering_unbalance_ratio` | Value determines each cluster's maximum capacity during CKMeans. A value of `0.5` (i.e., 50%) means that each cluster will have exactly half of all sinks for a specific region (half for each branch). The default value is `0.6`, and the allowed values are floats `[0, 1.0]`. |
+| `-sink_clustering_enable` | Enables pre-clustering of sinks to create one level of sub-tree before building H-tree. Each cluster is driven by buffer which becomes end point of H-tree structure. |
+| `-sink_clustering_size` | Specifies the maximum number of sinks per cluster. The default value is `20`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-sink_clustering_max_diameter` | Specifies maximum diameter (in microns) of sink cluster. The default value is `50`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-balance_levels` | Attempt to keep a similar number of levels in the clock tree across non-register cells (e.g., clock-gate or inverter). The default value is `False`, and the allowed values are bool. |
+| `-clk_nets` | String containing the names of the clock roots. If this parameter is omitted, `cts` looks for the clock roots automatically. |
+| `-num_static_layers` | Set the number of static layers. The default value is `0`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-sink_clustering_buffer` | Set the sink clustering buffer(s) to be used. |
+| `-obstruction_aware` | Enables obstruction-aware buffering such that clock buffers are not placed on top of blockages or hard macros. This option may reduce legalizer displacement, leading to better latency, skew or timing QoR.  The default value is `False`, and the allowed values are bool. |
+| `-apply_ndr` | Applies 2X spacing non-default rule to all clock nets except leaf-level nets. The default value is `False`. |
+| `-no_insertion_delay` | Don't consider insertion delays in macro timing models in balancing latencies between macro cells and registers. This option prevents construction of separate clock trees for macro cells and registers.  The default value is `False`. |
+| `-use_dummy_load` | Applies dummy buffer or inverter cells at clock tree leaves to balance loads.  The default values is `False`. |
+| `-sink_buffer_max_cap_derate` | Use this option to control automatic buffer selection. To favor strong(weak) drive strength buffers use a small(large) value.  The default value is `0.01`, meaning that buffers are selected by derating max cap limit by 0.01. The value of 1.0 means no derating of max cap limit.  |
+| `-delay_buffer_derate` | This option is used with -insertion_delay option that balances latencies between macro cells and registers by inserting delay buffers.  The default values is `1.0`, meaning all needed delay buffers are inserted.  Value of 0.5 means only half of necessary delay buffers are inserted.  Value of 0.0 means no insertion of delay buffers. |
+
+### Report CTS
+
+Another command available from `cts` is `report_cts`. It is used to
+extract metrics after a successful `clock_tree_synthesis` run. These are:
+ 
+- Number of Clock Roots
+- Number of Buffers Inserted
+- Number of Clock Subnets
+- Number of Sinks.  
+
+```tcl
+report_cts 
+    [-out_file file]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-out_file` | The file to save `cts` reports. If this parameter is omitted, the report is streamed to `stdout` and not saved. |
+
+### Useful Developer Commands
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/TritonCTS.cpp) or the [swig file](./src/TritonCTS.i).
+
+| Command Name | Description |
+| ----- | ----- | 
+| `clock_tree_synthesis_debug` | Option to plot the CTS to GUI. |
+
+## Example scripts
+
+```tcl
+clock_tree_synthesis -root_buf "BUF_X4" \
+                     -buf_list "BUF_X4" \
+                     -wire_unit 20
+report_cts "file.txt"
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out
+[GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+cts) about this tool.
+
+## References
+
+1.   [LEMON](https://lemon.cs.elte.hu/trac/lemon) - **L**ibrary for
+    **E**fficient **M**odeling and **O**ptimization in **N**etworks
+1.  Kahng, A. B., Li, J., & Wang, L. (2016, November). Improved flop tray-based design implementation for power reduction. In 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 1-8). IEEE. [(.pdf)](https://vlsicad.ucsd.edu/Publications/Conferences/344/c344.pdf)
+
+## Authors
+
+TritonCTS 2.0 is written by Mateus Fogaça, PhD student in the Graduate
+Program on Microelectronics from the Federal University of Rio Grande do Sul
+(UFRGS), Brazil. Mr. Fogaça's advisor is Prof. Ricardo Reis.
+
+Many guidance provided by (alphabetic order):
+-  Andrew B. Kahng
+-  Jiajia Li
+-  Kwangsoo Han
+-  Tom Spyrou
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.
+

data/markdown/OR_userguide/OR_dpl_README.md

@@ -0,0 +1,177 @@
+# Detailed Placement
+
+The detailed placement module in OpenROAD (`dpl`) is based on OpenDP, or 
+Open-Source Detailed Placement Engine. Its key features are: 
+
+-   Fence region.
+-   Fragmented ROWs.
+
+## Commands
+
+### Detailed Placement
+
+The `detailed_placement` command performs detailed placement of instances
+to legal locations after global placement.
+
+```tcl
+detailed_placement
+    [-max_displacement disp|{disp_x disp_y}]
+    [-disallow_one_site_gaps]
+    [-report_file_name filename]
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-max_displacement` | Max distance that an instance can be moved (in microns) when finding a site where it can be placed. Either set one value for both directions or set `{disp_x disp_y}` for individual directions. The default values are `{0, 0}`, and the allowed values within are integers `[0, MAX_INT]`. |
+| `-disallow_one_site_gaps` | Disable one site gap during placement check. |
+| `-report_file_name` | File name for saving the report to (e.g. `report.json`. |
+
+### Set Placement Padding
+
+The `set_placement_padding` command sets left and right padding in multiples
+of the row site width. Use the `set_placement_padding` command before
+legalizing placement to leave room for routing. Use the `-global` flag
+for padding that applies to all instances. Use  `-instances`
+for instance-specific padding.  The instances `insts` can be a list of instance
+names, or an instance object returned by the SDC `get_cells` command. To
+specify padding for all instances of a common master, use the `-filter`
+"ref_name == <name>" option to `get_cells`.
+
+```tcl
+set_placement_padding   
+    -global|-masters masters|-instances insts
+    [-right site_count]
+    [-left site_count]
+```
+
+#### Options
+
+```{warning}
+Either one of these flags must be set: `-global | -masters | -instances`.
+The order of preference is `global > masters > instances`
+```
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-global` | Set padding globally using `left` and `right` values. |
+| `-masters` |  Set padding only for these masters using `left` and `right` values. | 
+| `-instances` | For `-instances`, you will set padding only for these insts using `left` and `right` values. |
+| `-left` | Left padding (in site count). |
+| `-right` | Right padding (in site count). |
+| `instances` | Set padding for these list of instances. Not to be confused with the `-instances` switch above. |
+
+### Filler Placement
+
+The `filler_placement` command fills gaps between detail-placed instances
+to connect the power and ground rails in the rows. `filler_masters` is a
+list of master/macro names to use for filling the gaps. Wildcard matching
+is supported, so `FILL*` will match, e.g., `FILLCELL_X1 FILLCELL_X16 FILLCELL_X2
+FILLCELL_X32 FILLCELL_X4 FILLCELL_X8`.  To specify a different naming prefix
+from `FILLER_` use `-prefix <new prefix>`.
+
+```tcl 
+filler_placement
+    [-prefix prefix]
+    filler_masters
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-prefix` | Prefix to name the filler cells. The default value is `FILLER_`. |
+| `filler_masters` | Filler master cells. | 
+
+### Remove Fillers
+
+This command removes all filler cells.
+
+```tcl
+remove_fillers 
+```
+
+No arguments are needed for this function. 
+
+### Check Placement
+
+The `check_placement` command checks the placement legality. It returns
+`0` if the placement is legal.
+
+```tcl
+check_placement
+    [-verbose]
+    [-disallow_one_site_gaps]
+    [-report_filename filename]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-verbose` | Enable verbose logging. |
+| `-disallow_one_site_gaps` | Disable one site gap during placement check. |
+| `-report_file_name` | File name for saving the report to (e.g. `report.json`. |
+
+### Optimize Mirroring
+
+The `optimize_mirroring` command mirrors instances about the Y axis in
+a weak attempt to reduce the total half-perimeter wirelength (HPWL).
+
+```tcl
+optimize_mirroring
+```
+
+No arguments are needed for this function. 
+
+### Useful Developer Commands
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/Opendp.cpp) or the [swig file](./src/Opendp.i).
+
+| Command Name | Description |
+| ----- | ----- |
+| `detailed_placement_debug` | Debug detailed placement. |
+| `get_masters_arg` | Get masters from a design. |
+| `get_inst_bbox` | Get bounding box of an instance. |
+| `get_inst_grid_bbox` | Get grid bounding box of an instance. |
+| `format_grid` | Format grid (takes in length `x` and site width `w` as inputs). |
+| `get_row_site` | Get row site name.
+
+## Example scripts
+
+Examples scripts demonstrating how to run `dpl` on a sample design of `aes` as follows:
+
+```shell
+./test/aes.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. Refer to this [section](../../README.md#regression-tests) for more information.
+
+Simply run the following script: 
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+opendp+in%3Atitle)
+about this tool.
+
+## Authors
+
+-   SangGi Do and Mingyu Woo (respective Ph. D. advisors: Seokhyeong Kang,
+    Andrew B. Kahng).
+-   Rewrite and port to OpenDB/OpenROAD by James Cherry, Parallax Software
+
+## References
+1. Do, S., Woo, M., & Kang, S. (2019, May). Fence-region-aware mixed-height standard cell legalization. In Proceedings of the 2019 on Great Lakes Symposium on VLSI (pp. 259-262). [(.pdf)](https://dl.acm.org/doi/10.1145/3299874.3318012)
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_drt_README.md

@@ -0,0 +1,239 @@
+# Detailed Routing
+
+The Detailed Routing (`drt`) module in OpenROAD is based on the open-source
+detailed router, TritonRoute. TritonRoute consists of several main 
+building blocks, including pin access analysis, track assignment,
+initial detailed routing,  search and repair, and a DRC engine.
+The initial development of the
+[router](https://vlsicad.ucsd.edu/Publications/Conferences/363/c363.pdf)
+is inspired by the [ISPD-2018 initial detailed routing
+contest](http://www.ispd.cc/contests/18/).  However, the current framework
+differs and is built from scratch, aiming for an industrial-oriented scalable
+and flexible flow.
+
+TritonRoute provides industry-standard LEF/DEF interface with
+support of [ISPD-2018](http://www.ispd.cc/contests/18/) and
+[ISPD-2019](http://www.ispd.cc/contests/19/) contest-compatible route
+guide format.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Detailed Route
+
+```tcl
+detailed_route 
+    [-output_maze filename]
+    [-output_drc filename]
+    [-output_cmap filename]
+    [-output_guide_coverage filename]
+    [-drc_report_iter_step step]
+    [-db_process_node name]
+    [-disable_via_gen]
+    [-droute_end_iter iter]
+    [-via_in_pin_bottom_layer layer]
+    [-via_in_pin_top_layer layer]
+    [-or_seed seed]
+    [-or_k_ k]
+    [-bottom_routing_layer layer]
+    [-top_routing_layer layer]
+    [-verbose level]
+    [-distributed]
+    [-remote_host rhost]
+    [-remote_port rport]
+    [-shared_volume vol]
+    [-cloud_size sz]
+    [-clean_patches]
+    [-no_pin_access]
+    [-min_access_points count]
+    [-save_guide_updates]
+    [-repair_pdn_vias layer]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-output_maze` | Path to output maze log file (e.g. `output_maze.log`). |
+| `-output_drc` | Path to output DRC report file (e.g. `output_drc.rpt`). |
+| `-output_cmap` | Path to output congestion map file (e.g. `output.cmap`). |
+| `-output_guide_coverage` | Path to output guide coverage file (e.g. `sample_coverage.csv`). |
+| `-drc_report_iter_step` | Report DRC on each iteration which is a multiple of this step. The default value is `0`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-db_process_node` | Specify the process node. |
+| `-disable_via_gen` | Option to diable via generation with bottom and top routing layer. The default value is disabled. | 
+| `-droute_end_iter` | Number of detailed routing iterations. The default value is `-1`, and the allowed values are integers `[1, 64]`. |
+| `-via_in_pin_bottom_layer` | Via-in pin bottom layer name. |
+| `-via_in_pin_top_layer` | Via-in pin top layer name. |
+| `-or_seed` | Refer to developer arguments [here](#developer-arguments). |
+| `-or_k` | Refer to developer arguments [here](#developer-arguments). |
+| `-bottom_routing_layer` | Bottommost routing layer name. |
+| `-top_routing_layer` | Topmost routing layer name. |
+| `-verbose` | Sets verbose mode if the value is greater than 1, else non-verbose mode (must be integer, or error will be triggered.) |
+| `-distributed` | Refer to distributed arguments [here](#distributed-arguments). |
+| `-clean_patches` | Clean unneeded patches during detailed routing. | 
+| `-no_pin_access` | Disables pin access for routing. |
+| `-min_access_points` | Minimum access points for standard cell and macro cell pins. | 
+| `-save_guide_updates` | Flag to save guides updates. |
+| `-repair_pdn_vias` | This option is used for PDKs where M1 and M2 power rails run in parallel. |
+
+#### Developer arguments
+
+Some arguments that are helpful for developers are listed here. 
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-or_seed` | Random seed for the order of nets to reroute. The default value is `-1`, and the allowed values are integers `[0, MAX_INT]`. | 
+| `-or_k` | Number of swaps is given by $k * sizeof(rerouteNets)$. The default value is `0`, and the allowed values are integers `[0, MAX_INT]`. |
+
+### Detailed Route Debugging
+
+The following command and arguments are useful when debugging error
+messages from `drt` and to understand its behavior.
+
+```tcl
+detailed_route_debug 
+    [-pa]
+    [-ta]
+    [-dr]
+    [-maze]
+    [-net name]
+    [-pin name]
+    [-worker x y]
+    [-iter iter]
+    [-pa_markers]
+    [-dump_dr]
+    [-dump_dir dir]
+    [-pa_edge]
+    [-pa_commit]
+    [-write_net_tracks]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-pa` | Enable debug for pin access. |
+| `-ta` | Enable debug for track assignment. |
+| `-dr` | Enable debug for detailed routing. |
+| `-maze` | Enable debug for maze routing. | 
+| `-net` | Enable debug for net name. |
+| `-pin` | Enable debug for pin name. |
+| `-worker` | Debugs routes that pass through the point `{x, y}`. |
+| `-iter` | Specifies the number of debug iterations. The default value is `0`, and the accepted values are integers `[0, MAX_INT`. |
+| `-pa_markers` | Enable pin access markers. |
+| `-dump_dr` | Filename for detailed routing dump. |
+| `-dump_dir` | Directory for detailed routing dump. |
+| `-pa_edge` | Enable visibility of pin access edges. |
+| `-pa_commit` | Enable visibility of pin access commits. |
+| `-write_net_tracks` | Enable writing of net track assigments. |
+
+### Check Pin Access 
+
+```tcl
+pin_access
+    [-db_process_node name]
+    [-bottom_routing_layer layer]
+    [-top_routing_layer layer]
+    [-min_access_points count]
+    [-verbose level]
+    [-distributed]
+    [-remote_host rhost]
+    [-remote_port rport]
+    [-shared_volume vol]
+    [-cloud_size sz]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-db_process_node` | Specify process node. |
+| `-bottom_routing_layer` | Bottommost routing layer. |
+| `-top_routing_layer` | Topmost routing layer. |
+| `-min_access_points` | Minimum number of access points per pin. |
+| `-verbose` | Sets verbose mode if the value is greater than 1, else non-verbose mode (must be integer, or error will be triggered.) |
+| `-distributed` | Refer to distributed arguments [here](#distributed-arguments). |
+
+### Distributed arguments
+
+We have compiled all distributed arguments in this section.
+
+```{note}
+Additional setup is required. Please refer to this [guide](./doc/Distributed.md).
+```
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-distributed` | Enable distributed mode with Kubernetes and Google Cloud. |
+| `-remote_host` | The host IP. |
+| `-remote_port` | The value of the port to access from. |
+| `-shared_volume` | The mount path of the nfs shared folder. |
+| `-cloud_size` | The number of workers. |
+
+### Useful developer functions
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/TritonRoute.cpp) or the [swig file](./src/TritonRoute.i).
+
+| Function Name | Description |
+| ----- | ----- |
+| `detailed_route_set_default_via` | Set default via. |
+| `detailed_route_set_unidirectional_layer` | Set unidirectional layer. |
+| `step_dr` | Refer to function `detailed_route_step_drt`. | 
+| `check_drc` | Refer to function `check_drc_cmd`. |
+
+
+
+## Example scripts
+
+Example script demonstrating how to run TritonRoute on a sample design of `gcd`
+in the Nangate45 technology node.
+
+```shell
+# single machine example 
+./test/gcd_nangate45.tcl
+
+# distributed example
+./test/gcd_nangate45_distributed.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests). 
+
+Simply run the following script: 
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+tritonroute+in%3Atitle)
+about this tool.
+
+## References
+
+Please cite the following paper(s) for publication:
+
+1.   A. B. Kahng, L. Wang and B. Xu, "TritonRoute: The Open Source Detailed
+    Router", IEEE Transactions on Computer-Aided Design of Integrated Circuits
+    and Systems (2020), doi:10.1109/TCAD.2020.3003234. [(.pdf)](https://ieeexplore.ieee.org/ielaam/43/9358030/9120211-aam.pdf)
+1.   A. B. Kahng, L. Wang and B. Xu, "The Tao of PAO: Anatomy of a Pin Access
+    Oracle for Detailed Routing", Proc. ACM/IEEE Design Automation Conf., 2020,
+    pp. 1-6. [(.pdf)](https://vlsicad.ucsd.edu/Publications/Conferences/377/c377.pdf)
+
+## Authors
+
+TritonRoute was developed by graduate students Lutong Wang and
+Bangqi Xu from UC San Diego, and serves as the detailed router in the
+[OpenROAD](https://theopenroadproject.org/) project.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_fin_README.md

@@ -0,0 +1,92 @@
+# Metal fill
+
+This module inserts floating metal fill shapes to meet metal density
+design rules while obeying DRC constraints. It is driven by a `json`
+configuration file.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Density Fill
+
+```tcl
+density_fill
+    [-rules rules_file]
+    [-area {lx ly ux uy}]
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-rules` | Specify `json` rule file. |
+| `-area` | Optional. If not specified, the core area will be used. |
+
+## Example scripts
+
+The rules `json` file controls fill and you can see an example
+[here](https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/platforms/sky130hd/fill.json).
+
+The schema for the `json` is:
+
+```json
+{
+  "layers": {
+    "<group_name>": {
+      "layers": "<list of integer gds layers>",
+      "names": "<list of name strings>",
+      "opc": {
+        "datatype":  "<list of integer gds datatypes>",
+        "width":   "<list of widths in microns>",
+        "height":   "<list of heightsin microns>",
+        "space_to_fill": "<real: spacing between fills in microns>",
+        "space_to_non_fill": "<real: spacing to non-fill shapes in microns>",
+        "space_line_end": "<real: spacing to end of line in microns>"
+      },
+      "non-opc": {
+        "datatype":  "<list of integer gds datatypes>",
+        "width":   "<list of widths in microns>",
+        "height":   "<list of heightsin microns>",
+        "space_to_fill": "<real: spacing between fills in microns>",
+        "space_to_non_fill": "<real: spacing to non-fill shapes in microns>"
+      }
+    }, ...
+  }
+}
+```
+
+The `opc` section is optional depending on your process.
+
+The width/height lists are effectively parallel arrays of shapes to try
+in left to right order (generally larger to smaller).
+
+The layer grouping is for convenience. For example in some technologies many
+layers have similar rules so it is convenient to have a `Mx`, `Cx` group.
+
+This all started out in `klayout` so there are some obsolete fields that the
+parser accepts but ignores (e.g., `space_to_outline`).
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests). 
+
+Simply run the following script: 
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+metal%20fill+in%3Atitle)
+about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_gpl_README.md

@@ -0,0 +1,243 @@
+# Global Placement
+
+The global placement module in OpenROAD (`gpl`) is based on the open-source
+RePlAce tool, from the paper "Advancing Solution Quality and Routability Validation
+in Global Placement".
+
+Features:
+
+-   Analytic and nonlinear placement algorithm. Solves
+    electrostatic force equations using Nesterov's method.
+    ([link](https://cseweb.ucsd.edu/~jlu/papers/eplace-todaes14/paper.pdf))
+-   Verified with various commercial technologies and research enablements using OpenDB
+    (7/14/16/28/45/55/65nm).
+-   Verified deterministic solution generation with various compilers and OS.
+-   Supports Mixed-size placement mode.
+
+| <img src="./doc/image/adaptec2.inf.gif" width=350px> | <img src="./doc/image/coyote_movie.gif" width=400px> |
+|:--:|:--:|
+| Visualized examples from ISPD 2006 contest; adaptec2.inf |Real-world Design: Coyote (TSMC16 7.5T) |
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Global Placement
+
+When using the `-timing_driven` flag, `gpl` does a virtual `repair_design` 
+to find slacks and
+weight nets with low slack. It adjusts the worst slacks (modified with 
+`-timing_driven_nets_percentage`) using a multiplier (modified with 
+`-timing_driven_net_weight_max`). The multiplier
+is scaled from the full value for the worst slack, to 1.0 at the
+`timing_driven_nets_percentage` point. Use the `set_wire_rc` command to set
+resistance and capacitance of estimated wires used for timing.
+
+```
+global_placement
+    [-timing_driven]
+    [-routability_driven]
+    [-skip_initial_place]
+    [-incremental]
+    [-bin_grid_count grid_count]
+    [-density target_density]
+    [-init_density_penalty init_density_penalty]
+    [-init_wirelength_coef init_wirelength_coef]
+    [-min_phi_coef min_phi_conef]
+    [-max_phi_coef max_phi_coef]
+    [-overflow overflow]
+    [-initial_place_max_iter initial_place_max_iter]
+    [-initial_place_max_fanout initial_place_max_fanout]
+    [-pad_left pad_left]
+    [-pad_right pad_right]
+    [-verbose_level level]
+    [-force_cpu]
+    [-skip_io]
+    [-routability_check_overflow routability_check_overflow]
+    [-routability_max_density routability_max_density]
+    [-routability_max_bloat_iter routability_max_bloat_iter]
+    [-routability_max_inflation_iter routability_max_inflation_iter]
+    [-routability_target_rc_metric routability_target_rc_metric]
+    [-routability_inflation_ratio_coef routability_inflation_ratio_coef]
+    [-routability_pitch_scale routability_pitch_scale]
+    [-routability_max_inflation_ratio routability_max_inflation_ratio]
+    [-routability_rc_coefficients routability_rc_coefficients]
+    [-timing_driven_net_reweight_overflow]
+    [-timing_driven_net_weight_max]
+    [-timing_driven_nets_percentage]
+```
+
+#### General Arguments
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-timing_driven` | Enable timing-driven mode. See [link](#timing-driven-arguments) for timing-specific arguments. |
+| `-routability_driven` | Enable routability-driven mode. See [link](#routability-driven-arguments) for routability-specific arguments. |
+| `-skip_initial_place` | Skip the initial placement (Biconjugate gradient stabilized, or BiCGSTAB solving) before Nesterov placement. Initial placement improves HPWL by ~5% on large designs. Equivalent to `-initial_place_max_iter 0`. | 
+| `-incremental` | Enable the incremental global placement. Users would need to tune other parameters (e.g., `init_density_penalty`) with pre-placed solutions. | 
+| `-bin_grid_count` | Set bin grid's counts. The internal heuristic defines the default value. Allowed values are integers `[64,128,256,512,...]`. |
+| `-density` | Set target density. The default value is `0.7` (i.e., 70%). Allowed values are floats `[0, 1]`. |
+| `-init_density_penalty` | Set initial density penalty. The default value is `8e-5`. Allowed values are floats `[1e-6, 1e6]`. |
+| `-init_wirelength_coef` | Set initial wirelength coefficient. The default value is `0.25`. Allowed values are floats. |
+| `-min_phi_coef` | Set `pcof_min` ($\mu_k$ Lower Bound). The default value is `0.95`. Allowed values are floats `[0.95, 1.05]`. |
+| `-max_phi_coef` | Set `pcof_max` ($\mu_k$ Upper Bound). Default value is 1.05. Allowed values are `[1.00-1.20, float]`. |
+| `-overflow` | Set target overflow for termination condition. The default value is `0.1`. Allowed values are floats `[0, 1]`. |
+| `-initial_place_max_iter` | Set maximum iterations in the initial place. The default value is 20. Allowed values are integers `[0, MAX_INT]`. |
+| `-initial_place_max_fanout` | Set net escape condition in initial place when $fanout \geq initial\_place\_max\_fanout$. The default value is 200. Allowed values are integers `[1, MAX_INT]`. |
+| `-pad_left` | Set left padding in terms of number of sites. The default value is 0, and the allowed values are integers `[1, MAX_INT]` |
+| `-pad_right` | Set right padding in terms of number of sites. The default value is 0, and the allowed values are integers `[1, MAX_INT]` |
+| `-verbose_level` | Set verbose level for `gpl`. The default value is 1. Allowed values are integers `[0, 5]`. |
+| `-force_cpu` | Force to use the CPU solver even if the GPU is available. |
+| `-skip_io` | Flag to ignore the IO ports when computing wirelength during placement. The default value is False, allowed values are boolean. |
+
+#### Routability-Driven Arguments
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-routability_check_overflow` | Set overflow threshold for routability mode. The default value is `0.2`, and the allowed values are floats `[0, 1]`. |
+| `-routability_max_density` | Set density threshold for routability mode. The default value is `0.99`, and the allowed values are floats `[0, 1]`. |
+| `-routability_max_bloat_iter` | Set bloat iteration threshold for routability mode. The default value is `1`, and the allowed values are integers `[1, MAX_INT]`.|
+| `-routability_max_inflation_iter` | Set inflation iteration threshold for routability mode. The default value is `4`, and the allowed values are integers `[1, MAX_INT]`. |
+| `-routability_target_rc_metric` | Set target RC metric for routability mode. The default value is `1.25`, and the allowed values are floats. |
+| `-routability_inflation_ratio_coef` | Set inflation ratio coefficient for routability mode. The default value is `2.5`, and the allowed values are floats. |
+| `-routability_max_inflation_ratio` | Set inflation ratio threshold for routability mode. The default value is `2.5`, and the allowed values are floats. |
+| `-routability_rc_coefficients` | Set routability RC coefficients. It comes in the form of a Tcl List `{k1, k2, k3, k4}`. The default value for each coefficient is `{1.0, 1.0, 0.0, 0.0}` respectively, and the allowed values are floats. |
+
+#### Timing-Driven Arguments
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-timing_driven_net_reweight_overflow` | Set overflow threshold for timing-driven net reweighting. Allowed value is a Tcl list of integers where each number is `[0, 100]`. |
+| `-timing_driven_net_weight_max` | Set the multiplier for the most timing-critical nets. The default value is `1.9`, and the allowed values are floats. |
+| `-timing_driven_nets_percentage` | Set the reweighted percentage of nets in timing-driven mode. The default value is 10. Allowed values are floats `[0, 100]`. |
+
+
+### Useful developer functions
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/replace.cpp) or the [swig file](./src/replace.i).
+
+```tcl
+# debugging global placement 
+global_placement_debug -pause -update -inst -draw_bins -initial
+
+# adds padding and gets global placement uniform target density
+get_global_placement_uniform_density -pad_left -pad_right 
+```
+
+### Cluster Flops
+
+Cluster single bit flops into multi-bit flops.
+
+```
+cluster_flops
+    [-tray_weight tray_weight]
+    [-timing_weight timing_weight]
+    [-max_split_size max_split_size]
+    [-num_paths num_paths]
+```
+
+#### General Arguments
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-tray_weight` | Set the weighting factor for tray cost (recommended to be `[20.0, float]`). |
+| `-timing_weight` | Set the weighting factor for timing-critical paths in (recommended to be `[1.0. float]`). |
+| `-max_split_size` | The maximum size of a single pointset after running the pointset decomposition algorithm for runtime improvement (default = 250). |
+| `num_paths` | Number of timing-critical paths to consider (default = 0). |
+
+
+## Example Scripts
+
+Example scripts demonstrating how to run `gpl` on a sample design on `core01` as follows:
+
+```shell
+./test/core01.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## Using the Python interface to gpl
+
+This API tries to stay close to the API defined in `C++` class `Replace`
+that is located [here](include/gpl/Replace.h).
+
+When initializing a design, a sequence of Python commands might look like
+the following:
+
+```python
+from openroad import Design, Tech
+tech = Tech()
+tech.readLef(...)
+design = Design(tech)
+design.readDef(...)
+gpl = design.getReplace()
+```    
+
+Here is an example of some options / configurations to the global placer.
+(See [Replace.h](include/gpl/Replace.h) for a complete list)
+
+```python
+gpl.setInitialPlaceMaxIter(iter)
+gpl.setSkipIoMode(skip_io)
+gpl.setTimingDrivenMode(timing_driven)
+gpl.setTimingNetWeightMax(weight)
+```
+
+There are some useful Python functions located in the file
+[grt_aux.py](test/grt_aux.py) but these are not considered a part of the *final*
+API and they may change.
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+replace+in%3Atitle)
+about this tool.
+
+## References
+
+-   C.-K. Cheng, A. B. Kahng, I. Kang and L. Wang, "RePlAce: Advancing
+    Solution Quality and Routability Validation in Global Placement", IEEE
+    Transactions on Computer-Aided Design of Integrated Circuits and Systems,
+    38(9) (2019), pp. 1717-1730. [(.pdf)](https://vlsicad.ucsd.edu/Publications/Journals/j126.pdf)
+-   J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-H. Huang, C.-C. Teng and
+    C.-K. Cheng, "ePlace: Electrostatics based Placement using Fast Fourier
+    Transform and Nesterov's Method", ACM TODAES 20(2) (2015), article 17. [(.pdf)](https://cseweb.ucsd.edu/~jlu/papers/eplace-todaes14/paper.pdf)
+-   J. Lu, H. Zhuang, P. Chen, H. Chang, C.-C. Chang, Y.-C. Wong, L. Sha,
+    D. J.-H. Huang, Y. Luo, C.-C. Teng and C.-K. Cheng, "ePlace-MS:
+    Electrostatics based Placement for Mixed-Size Circuits", IEEE TCAD 34(5)
+    (2015), pp. 685-698. [(.pdf)](https://cseweb.ucsd.edu/~jlu/papers/eplace-ms-tcad14/paper.pdf)
+-   A. B. Kahng, J. Li and L. Wang,   
+    "Improved Flop Tray-Based Design Implementation for Power Reduction",   
+    IEEE/ACM ICCAD, 2016, pp. 20:1-20:8.   
+-   The timing-driven mode has been implemented by
+    Mingyu Woo (only available in [legacy repo in standalone
+    branch](https://github.com/The-OpenROAD-Project/RePlAce/tree/standalone).)
+-   The routability-driven mode has been implemented by Mingyu Woo.
+-   Timing-driven mode re-implementation is ongoing with the current
+    clean-code structure.
+
+ ## Authors
+
+-   Authors/maintainer since Jan 2020: Mingyu Woo (Ph.D. Advisor:
+    Andrew. B. Kahng)
+-   Original open-sourcing of RePlAce: August 2018, by Ilgweon Kang
+    (Ph.D. Advisor: Chung-Kuan Cheng), Lutong Wang (Ph.D. Advisor: Andrew
+    B. Kahng), and Mingyu Woo (Ph.D. Advisor: Andrew B. Kahng).
+-   Also thanks to Dr. Jingwei Lu for open-sourcing the previous
+    ePlace-MS/ePlace project code.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

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+# Global Routing
+
+The global routing module in OpenROAD (`grt`) is based on FastRoute, an
+open-source global router originally derived from Iowa State University's
+FastRoute4.1 algorithm.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Global Route
+
+```tcl
+global_route 
+    [-guide_file out_file]
+    [-congestion_iterations iterations]
+    [-congestion_report_file file_name]
+    [-congestion_report_iter_step steps]
+    [-grid_origin {x y}]
+    [-critical_nets_percentage percent]
+    [-allow_congestion]
+    [-verbose]
+    [-start_incremental]
+    [-end_incremental]
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-guide_file` | Set the output guides file name (e.g., `route.guide`). |
+| `-congestion_iterations` | Set the number of iterations made to remove the overflow of the routing. The default value is `50`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-congestion_report_file` | Set the file name to save the congestion report. The file generated can be read by the DRC viewer in the GUI (e.g., `report_file.rpt`). |
+| `-congestion_report_iter_step` | Set the number of iterations to report. The default value is `0`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-grid_origin` | Set the (x, y) origin of the routing grid in DBU. For example, `-grid_origin {1 1}` corresponds to the die (0, 0) + 1 DBU in each x--, y- direction. |
+| `-critical_nets_percentage` | Set the percentage of nets with the worst slack value that are considered timing critical, having preference over other nets during congestion iterations (e.g. `-critical_nets_percentage 30`). The default value is `0`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-allow_congestion` | Allow global routing results to be generated with remaining congestion. The default is false. |
+| `-verbose` | This flag enables the full reporting of the global routing. |
+| `-start_incremental` | This flag initializes the GRT listener to get the net modified. The default is false. |
+| `-end_incremental` | This flag run incremental GRT with the nets modified. The default is false. |
+
+### Set Routing Layers
+
+```tcl
+set_routing_layers 
+    [-signal min-max]
+    [-clock min-max]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-signal` | Set the min and max routing signal layer (names) in this format "%s-%s". |
+| `-clock` | Set the min and max routing clock layer (names) in this format "%s-%s". |
+
+Example: `set_routing_layers -signal Metal2-Metal10 -clock Metal6-Metal9`
+
+### Set Macro Extension
+
+```tcl
+set_macro_extension extension
+```
+
+#### Options
+
+| Argument Name | Description | 
+| ----- | ----- |
+| `extension` | Number of `GCells` added to the blockage boundaries from macros. A `GCell` is typically defined in terms of `Mx` routing tracks.  The default `GCell` size is 15 `M3` pitches. | 
+
+Example: `set_macro_extension 2`
+
+### Set Pin Offset
+
+```tcl
+set_pin_offset offset 
+```
+
+#### Options
+
+| Argument Name | Description | 
+| ----- | ----- |
+| `offset` | Pin offset in microns (must be a positive integer). | 
+
+### Set Global Routing Layer Adjustment
+
+The `set_global_routing_layer_adjustment` command sets routing resource
+adjustments in the routing layers of the design.  Such adjustments reduce the number of
+routing tracks that the global router assumes to exist. This promotes the spreading of routing
+and reduces peak congestion, to reduce challenges for detailed routing.
+
+```tcl
+set_global_routing_layer_adjustment layer adjustment
+```
+
+#### Options
+
+| Argument Name | Description | 
+| ----- | ----- |
+| `layer` | Integer for the layer number (e.g. for M1 you would use 1). |
+| `adjustment` | Float indicating the percentage reduction of each edge in the specified layer. |
+
+You can set adjustment for a
+specific layer, e.g., `set_global_routing_layer_adjustment Metal4 0.5` reduces
+the routing resources of routing layer `Metal4` by 50%.  You can also set adjustment
+for all layers at once using `*`, e.g., `set_global_routing_layer_adjustment * 0.3` reduces the routing resources of all routing layers by 30%.  And, you can
+also set resource adjustment for a layer range, e.g.: `set_global_routing_layer_adjustment
+Metal4-Metal8 0.3` reduces the routing resources of routing layers  `Metal4`,
+`Metal5`, `Metal6`, `Metal7` and `Metal8` by 30%.
+
+### Set Routing Alpha
+
+By default the global router uses heuristic rectilinear Steiner minimum
+trees (RSMTs) as an initial basis to construct route guides. An RSMT
+tries to minimize the total wirelength needed to connect a given set
+of pins.  The Prim-Dijkstra heuristic is an alternative net topology
+algorithm that supports a trade-off between total wirelength and maximum
+path depth from the net driver to its loads. The `set_routing_alpha`
+command enables the Prim/Dijkstra algorithm and sets the alpha parameter
+used to trade-off wirelength and path depth.  Alpha is between 0.0
+and 1.0. When alpha is 0.0 the net topology minimizes total wirelength
+(i.e. capacitance).  When alpha is 1.0 it minimizes longest path between
+the driver and loads (i.e., maximum resistance).  Typical values are
+0.4-0.8. You can call it multiple times for different nets.
+
+```tcl
+set_routing_alpha 
+    [-net net_name] 
+    [-min_fanout fanout]
+    [-min_hpwl hpwl]
+    [-clock_nets]
+    alpha
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-net` | Net name. | 
+| `-min_fanout` | Set the minimum number for fanout. | 
+| `-min_hpwl` | Set the minimum half-perimetere wirelength (microns). | 
+| `-clock_nets` | Flag to set routing alpha for clock nets. The default value is `False`, and the allowed values are bools. |
+| `alpha` | Set the trade-off value between wirelength and path depth. The allowed values are floats `[0, 1]`. |
+
+Example: `set_routing_alpha -net clk 0.3` sets the alpha value of 0.3 for net *clk*.
+
+### Set Global Routing Region Adjustment
+
+```tcl
+set_global_routing_region_adjustment
+    {lower_left_x lower_left_y upper_right_x upper_right_y}
+    -layer layer 
+    -adjustment adjustment
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `lower_left_x`, `lower_left_y`, `upper_right_x` , `upper_right_y` | Bounding box to consider. |
+| `-layer` | Integer for the layer number (e.g. for M1 you would use 1). |
+| `-adjustment` | Float indicating the percentage reduction of each edge in the specified layer. |
+
+Example: `set_global_routing_region_adjustment {1.5 2 20 30.5} -layer Metal4 -adjustment 0.7`
+
+### Set Global Routing Randomness
+
+The randomized global routing shuffles the
+order of the nets and randomly subtracts or adds to the capacities of
+a random set of edges. 
+
+```tcl
+set_global_routing_random 
+    [-seed seed]
+    [-capacities_perturbation_percentage percent]
+    [-perturbation_amount value]
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-seed` | Sets the random seed (must be non-zero for randomization). |
+| `-capacities_perturbation_percentage` | Sets the percentage of edges whose capacities are perturbed. By default, the edge capacities are perturbed by adding or subtracting 1 (track) from the original capacity.  |
+| `-perturbation_amount` | Sets the perturbation value of the edge capacities. This option is only meaningful when `-capacities_perturbation_percentage` is used. |
+
+Example:
+`set_global_routing_random -seed 42 \
+  -capacities_perturbation_percentage 50 \
+  -perturbation_amount 2`
+
+### Set Specific Nets to Route
+
+The `set_nets_to_route` command defines a list of nets to route. Only the nets
+defined in this command are routed, leaving the remaining nets without any
+global route guides.
+
+```tcl
+set_nets_to_route 
+    net_names 
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `net_names` | Tcl list of set of nets (e.g. `{net1, net2}`). |
+
+### Repair Antennas
+
+The `repair_antennas` command checks the global routing for antenna
+violations and repairs the violations by inserting diodes near the
+gates of the violating nets.  By default the command runs only one
+iteration to repair antennas. Filler instances added by the
+`filler_placement` command should NOT be in the database when
+`repair_antennas` is called. 
+
+```tcl
+repair_antennas 
+    [diode_cell]
+    [-iterations iterations]
+    [-ratio_margin margin]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `diode_cell` | Diode cell to fix antenna violations. |
+| `-iterations` | Number of iterations. The default value is `1`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-ratio_margin` | Add a margin to the antenna ratios. The default value is `0`, and the allowed values are integers `[0, 100]`. |
+
+See LEF/DEF 5.8 Language Reference, Appendix C, "Calculating and
+Fixing Process Antenna Violations" for a [description](coriolis.lip6.fr/doc/lefdef/lefdefref/lefdefref.pdf) 
+of antenna violations.
+
+If no `diode_cell` argument is specified the LEF cell with class CORE, ANTENNACELL will be used.
+If any repairs are made the filler instances are remove and must be
+placed with the `filler_placement` command.
+
+If the LEF technology layer `ANTENNADIFFSIDEAREARATIO` properties are constant
+instead of PWL, inserting diodes will not improve the antenna ratios, 
+and thus, no
+diodes are inserted. The following warning message will be reported:
+
+```
+[WARNING GRT-0243] Unable to repair antennas on net with diodes.
+```
+
+### Write Global Routing Guides
+
+```tcl
+write_guides file_name
+```
+
+| Switch Name | Description |
+| ----- | ----- |
+| `file_name` | Guide file name. |
+
+Example: `write_guides route.guide`.
+
+### Estimate Global Routing Parasitics
+
+To estimate RC parasitics based on global route results, use the `-global_routing`
+option of the `estimate_parasitics` command.
+
+```{note}
+To see the function definition for `estimate_parasitics`, refer to 
+[Resizer docs](../rsz/README.md#estimate-parasitics).
+```
+
+```tcl
+estimate_parasitics -global_routing
+```
+
+### Plot Global Routing Guides
+
+The `draw_route_guides` command plots the route guides for a set of nets.
+To erase the route guides from the GUI, pass an empty list to this command:
+`draw_route_guides {}`.
+
+```tcl
+draw_route_guides 
+    net_names 
+    [-show_pin_locations]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `net_names` | Tcl list of set of nets (e.g. `{net1, net2}`). |
+| `-show_pin_locations` | Draw circles for the pin positions on the routing grid. |
+
+### Report Wirelength
+
+The `report_wire_length` command reports the wire length of the nets. Use the `-global_route`
+and the `-detailed_route` flags to report the wire length from global and detailed routing,
+respectively. If none of these flags are used, the tool will identify the state of the design
+and report the wire length accordingly.
+
+```tcl
+report_wire_length 
+    [-net net_list]
+    [-file file]
+    [-global_route]
+    [-detailed_route]
+    [-verbose]
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-net` | List of nets to report the wirelength. Use `*` to report the wire length for all nets of the design. |
+| `-file` | The name of the file for the wirelength report. |
+| `-global_route` | Report the wire length of the global routing. |
+| `-detailed_route` | Report the wire length of the detailed routing. |
+| `-verbose` | This flag enables the full reporting of the layer-wise wirelength information. |
+
+Example: `report_wire_length -net {clk net60} -global_route -detailed_route -verbose -file out.csv`
+
+### Debug Mode
+
+The `global_route_debug` command allows you to start a debug mode to view the status of the Steiner Trees.
+It also allows you to dump the input positions for the Steiner tree creation of a net.
+This must be used before calling the `global_route` command. 
+Set the name of the net and the trees that you want to visualize.
+
+```tcl
+global_route_debug 
+    [-st]
+    [-rst]
+    [-tree2D]
+    [-tree3D]
+    [-saveSttInput file_name]
+    [-net net_name]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-st` | Show the Steiner Tree generated by `stt`. |
+| `-rst` | Show the Rectilinear Steiner Tree generated by `grt`. |
+| `-tree2D` | Show the Rectilinear Steiner Tree generated by `grt` after the overflow iterations. |
+| `-tree3D` | Show the 3D Rectilinear Steiner Tree post-layer assignment. |
+| `-saveSttInput` | File name to save `stt` input of a net. |
+| `-net` | The name of the net name to be displayed. |
+
+## Example scripts
+
+Examples scripts demonstrating how to run FastRoute on a sample design of `gcd` as follows:
+
+```shell
+./test/gcd.tcl
+```
+
+### Read Global Routing Guides
+
+```tcl
+read_guides file_name 
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `file_name` | Path to global routing guide. | 
+
+### Useful developer functions
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/GlobalRouter.cpp) or the [swig file](./src/GlobalRouter.i).
+
+| Function Name | Description |
+| ----- | ----- |
+| `check_routing_layer` | Check if the layer is within the min/max routing layer specified. |
+| `parse_layer_name` | Get routing layer number from layer name |
+| `parse_layer_range` | Parses a range from `layer_range` argument of format (%s-%s). `cmd` argument is not used. |
+| `check_region` | Checks the defined region if its within the die area. |
+| `define_layer_range` | Provide a Tcl list of layers and automatically generate the min and max layers for signal routing. |
+| `define_clock_layer_range` | Provide a Tcl list of layers and automatically generate the min and max layers for clock routing. |
+| `have_detailed_route` | Checks if block has detailed route already. |
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests). 
+
+Simply run the following script: 
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## Using the Python interface to grt
+
+```{warning}
+The `Python` interface is currently in development and is subject to change.
+```
+
+The `Python` API tries to stay close to the API defined in the `C++` class
+`GlobalRouter` that is located [here](./include/grt/GlobalRouter.h)
+
+When initializing a design, a sequence of `Python` commands might look like
+the following:
+
+```python
+from openroad import Design, Tech
+tech = Tech()
+tech.readLef(...)
+design = Design(tech)
+design.readDef(...)
+gr = design.getGlobalRouter()
+```    
+
+Here are some options to the `global_route`
+command. (See `GlobalRouter.h` for a complete list)
+
+```python
+gr.setGridOrigin(x, y)                     # int, default 0,0
+gr.setCongestionReportFile(file_name)      # string
+gr.setOverflowIterations(n)                # int, default 50
+gr.setAllowCongestion(allowCongestion)     # boolean, default False
+gr.setCriticalNetsPercentage(percentage)   # float
+gr.setMinRoutingLayer(minLayer)            # int
+gr.setMaxRoutingLayer(maxLayer)            # int
+gr.setMinLayerForClock(minLayer)           # int
+gr.setMaxLayerForClock(maxLayer)           # int
+gr.setVerbose(v)                           # boolean, default False
+```
+
+and when ready to actually do the global route:
+
+```python
+gr.globalRoute(save_guides)                # boolean, default False
+```    
+
+If you have set `save_guides` to True, you can then save the guides in `file_name` with:
+
+```python
+design.getBlock().writeGuides(file_name)
+```
+
+You can find the index of a named layer with
+
+```python
+lindex = tech.getDB().getTech().findLayer(layer_name)
+```
+
+or, if you only have the `Python` design object
+
+```python
+lindex = design.getTech().getDB().getTech().findLayer(layer_name)
+```    
+
+Be aware that much of the error checking is done in `Tcl`, so that with
+the current `C++` / `Python` API, that might be an issue to deal
+with. There are also some useful `Python` functions located in the `grt_aux.py` [file](./test/grt_aux.py)
+but these are not considered a part of the *final* API and may be subject to change.
+
+## FAQs
+
+Check out
+[GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+fastroute+in%3Atitle)
+about this tool.
+
+## References
+
+-   Database comes from [OpenDB](https://github.com/The-OpenROAD-Project/OpenDB)
+-   [FastRoute 4.1 documentation](src/fastroute/README).  The FastRoute4.1
+    version was received from [Yue Xu](mailto:yuexu@iastate.edu) on June 15, 2019.
+-   Min Pan, Yue Xu, Yanheng Zhang and Chris Chu. "FastRoute: An Efficient and
+    High-Quality Global Router. VLSI Design, Article ID 608362, 2012."
+    Available [here](https://home.engineering.iastate.edu/~cnchu/pubs/j52.pdf).
+-   C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng and
+    D. Karger, "Prim-Dijkstra Tradeoffs for Improved Performance-Driven
+    Global Routing", IEEE Transactions on Computer-Aided Design of
+    Integrated Circuits and Systems 14(7) (1995), pp. 890-896. Available
+    [here](https://vlsicad.ucsd.edu/Publications/Journals/j18.pdf).
+
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_gui_README.md

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+# Graphical User Interface
+
+The graphical user interface can be access by launching OpenROAD with ``-gui`` or by opening it from the command-line with ``gui::show``.
+
+## Commands
+
+### Add buttons to the toolbar
+
+```
+create_toolbar_button [-name name]
+                      -text button_text
+                      -script tcl_script 
+                      [-echo]
+```
+
+Returns: name of the new button, either ``name`` or ``buttonX``.
+
+Options description:
+- ``button_text``: The text to put on the button.
+- ``tcl_script``: The tcl script to evaluate when the button is pressed.
+- ``name``: (optional) name of the button, used when deleting the button.
+- ``echo``: (optional) indicate that the commands in the ``tcl_script`` should be echoed in the log.
+
+To remove the button: 
+
+```
+gui::remove_toolbar_button name
+```
+
+### Add items to the menubar
+
+```
+create_menu_item [-name name]
+                 [-path menu_path]
+                 -text item_text
+                 -script tcl_script
+                 [-shortcut key_shortcut] 
+                 [-echo]
+```
+
+Returns: name of the new item, either ``name`` or ``actionX``.
+
+Options description:
+- ``item_text``: The text to put on the item.
+- ``tcl_script``: The tcl script to evaluate when the button is pressed.
+- ``name``: (optional) name of the item, used when deleting the item.
+- ``menu_path``: (optional) Menu path to place the new item in (hierarchy is separated by /), defaults to "Custom Scripts", but this can also be "Tools" or "New menu/New submenu".
+- ``key_shortcut``: (optional) key shortcut to trigger this item.
+- ``echo``: (optional) indicate that the commands in the ``tcl_script`` should be echoed in the log.
+
+To remove the item: 
+
+```
+gui::remove_menu_item name
+```
+
+
+### Save screenshot of layout
+
+This command can be both be used when the GUI is active and not active.
+
+```
+save_image [-resolution microns_per_pixel]
+           [-area {x0 y0 x1 y1}]
+           [-width width]
+           [-display_option {option value}]
+           filename
+```
+
+Options description:
+- ``filename`` path to save the image to.
+- ``x0, y0`` first corner of the layout area (in microns) to be saved, default is to save what is visible on the screen unless called when gui is not active and then it selected the whole block.
+- ``x1, y1`` second corner of the layout area (in microns) to be saved, default is to save what is visible on the screen unless called when gui is not active and then it selected the whole block.
+- ``microns_per_pixel`` resolution in microns per pixel to use when saving the image, default will match what the GUI has selected.
+- ``width`` width of the output image in pixels, default will be computed from the resolution. Cannot be used with ``-resolution``.
+- ``option`` specific setting for a display option to show or hide specific elements. For example, to hide metal1 ``-display_option {Layers/metal1 false}``, to show routing tracks ``-display_option {Tracks/Pref true}``, or to show everthing ``-display_option {* true}``.
+
+### Save screenshot of clock trees
+
+```
+save_clocktree_image filename
+                     -clock clock_name
+                     [-width width]
+                     [-height height]
+                     [-corner corner]
+```
+
+Options description:
+- ``filename`` path to save the image to.
+- ``-clock`` name of the clock to save the clocktree for.
+- ``-corner`` name of the timing corner to save the clocktree for, default to the first corner defined.
+- ``-height`` height of the image in pixels, defaults to the height of the GUI widget.
+- ``-width`` width of the image in pixels, defaults to the width of the GUI widget.
+
+### Selecting objects
+
+```
+select -type object_type
+       [-name glob_pattern]
+       [-filter attribute=value]
+       [-case_insensitive]
+       [-highlight group]
+```
+
+Returns: number of objects selected.
+
+Options description:
+- ``object_type``: name of the object type. For example, ``Inst`` for instances, ``Net`` for nets, and ``DRC`` for DRC violations.
+- ``glob_pattern``: (optional) filter selection by the specified name. For example, to only select clk nets ``*clk*``. Use ``-case_insensitive`` to filter based on case insensitive instead of case sensitive.
+- ``attribute=value``: (optional) filter selection based on the objects' properties. ``attribute`` represents the property's name and ``value`` the property's value. In case the property holds a collection (e. g. BTerms in a Net) or a table (e. g. Layers in a Generate Via Rule) ``value`` can be any element within those. A special case exists for checking whether a collection is empty or not by using the value ``CONNECTED``. This can be useful to select a specific group of elements (e. g. BTerms=CONNECTED will select only Nets connected to Input/Output Pins).
+- ``group``: (optional) add the selection to the specific highlighting group. Values can be 0 to 7.
+
+### Displaying timing cones
+
+```
+display_timing_cone pin
+                    [-fanin]
+                    [-fanout]
+                    [-off]
+```
+
+Options description:
+- ``pin``: name of the instance or block pin.
+- ``fanin``: (optional) display the fanin timing cone.
+- ``fanout``: (optional) display the fanout timing cone.
+- ``off``: (optional) remove the timing cone.
+
+### Limit drawing to specific nets
+
+```
+focus_net net
+          [-remove]
+          [-clear]
+```
+
+Options description:
+- ``pin``: name of the net.
+- ``remove``: (optional) removes the net from from the focus.
+- ``clear``: (optional) clears all nets from focus.
+
+## TCL functions
+
+### Support
+
+Determine is the GUI is active:
+
+```
+gui::enabled
+```
+
+Announce to the GUI that a design was loaded 
+(note: this is only needed when the design was loaded through the odb API and not via ``read_def`` or ``read_db``):
+
+```
+gui::design_created
+```
+
+To load the results of a DRC report:
+
+```
+gui::load_drc filename
+```
+
+### Opening and closing
+
+To open the GUI from the command-line (this command does not return until the GUI is closed):
+
+```
+gui::show
+gui::show script
+gui::show script interactive
+```
+
+Options description:
+- ``script`` TCL script to evaluate in the GUI.
+- ``interactive`` indicates if true the GUI should open in an interactive session (default), or if false that the GUI would execute the script and return to the terminal.
+
+To close the GUI and return to the command-line:
+
+```
+gui::hide
+```
+
+### Layout navigation
+
+To fit the whole layout in the window:
+
+```
+gui::fit
+```
+
+To zoom in our out to a specific region:
+
+```
+gui::zoom_to x0 y0 x1 y1
+```
+
+Options description:
+- ``x0, y0`` first corner of the layout area in microns.
+- ``x1, y1`` second corner of the layout area in microns.
+
+To zoom in the layout:
+
+```
+gui::zoom_in
+gui::zoom_in x y
+```
+
+Options description:
+- ``x, y`` new center of layout.
+
+To zoom out the layout:
+
+```
+gui::zoom_out
+gui::zoom_out x y
+```
+
+Options description:
+- ``x, y`` new center of layout.
+
+To move the layout to new area:
+
+```
+gui::center_at x y
+```
+
+Options description:
+- ``x, y`` new center of layout.
+
+To change the resolution to a specific value:
+
+```
+gui::set_resolution resolution
+```
+
+Options description:
+- ``resolution`` database units per pixel.
+
+### Selections
+
+To add a single net to the selected items:
+
+```
+gui::selection_add_net name
+```
+
+Options description:
+- ``name`` name of the net to add.
+
+To add several nets to the selected items:
+
+```
+gui::selection_add_nets name_regex
+```
+
+Options description:
+- ``name_regex`` regular expression of the net names to add.
+
+To add a single instance to the selected items:
+
+```
+gui::selection_add_inst name
+```
+
+Options description:
+- ``name`` name of the instance to add.
+
+To add several instances to the selected items:
+
+```
+gui::selection_add_insts name_regex
+```
+
+Options description:
+- ``name_regex`` regular expression of the instance names to add.
+
+To add items at a specific point or in an area:
+
+```
+gui::select_at x y
+gui::select_at x y append
+gui::select_at x0 y0 x1 y1
+gui::select_at x0 y0 x1 y1 append
+```
+
+Options description:
+- ``x, y`` point in the layout area in microns.
+- ``x0, y0`` first corner of the layout area in microns.
+- ``x1, y1`` second corner of the layout area in microns.
+- ``append`` if ``true`` (the default value) append the new selections to the current selection list, else replace the selection list with the new selections.
+
+To navigate through multiple selected items:
+
+```
+gui::select_next
+gui::select_previous
+```
+
+Returns: current index of the selected item.
+
+To clear the current set of selected items:
+
+```
+gui::clear_selections
+```
+
+To get the properties for the current selection in the Inspector:
+
+```
+gui::get_selection_property name
+```
+
+Options description:
+- ``name`` name of the property. For example, ``Type`` for object type or ``bbox`` for the bounding box of the object.
+
+To animate the current selection in the Inspector:
+
+```
+gui::selection_animate
+gui::selection_animate repeat
+```
+
+Options description:
+- ``repeat``: indicate how many times the animation should repeat, default value is 0 repeats. If the value is 0, the animation will repeat indefinitely.
+
+### Highlighting
+
+To highlight a net:
+
+```
+gui::highlight_net name
+gui::highlight_net name highlight_group
+```
+
+Options description:
+- ``name`` name of the net to highlight.
+- ``highlight_group`` group to add the highlighted net to, defaults to ``0``, valid groups are ``0 - 7``.
+
+To highlight an instance:
+
+```
+gui::highlight_inst name
+gui::highlight_inst name highlight_group
+```
+
+Options description:
+- ``name`` name of the instance to highlight.
+- ``highlight_group`` group to add the highlighted instance to, defaults to ``0``, valid groups are ``0 - 7``.
+
+To clear the highlight groups:
+
+```
+gui::clear_highlights
+gui::clear_highlights highlight_group
+```
+
+Options description:
+- ``highlight_group`` group to clear, defaults to ``0``, valid groups are ``-1 - 7``. Use ``-1`` to clear all groups.
+
+### Rulers
+
+To add a ruler to the layout:
+
+1. either press ``k`` and use the mouse to place it visually.
+To disable snapping for the ruler when adding, hold the ``Ctrl`` key, and to allow non-horizontal or vertical snapping when completing the ruler hold the ``Shift`` key.
+
+2. or use the command:
+
+```
+gui::add_ruler x0 y0 x1 y1
+gui::add_ruler x0 y0 x1 y1 label
+gui::add_ruler x0 y0 x1 y1 label name
+gui::add_ruler x0 y0 x1 y1 label name euclidian
+```
+
+Returns: name of the newly created ruler.
+
+Options description: 
+- ``x0, y0`` first end point of the ruler in microns.
+- ``x1, y1`` second end point of the ruler in microns.
+- ``label`` text label for the ruler.
+- ``name`` name of the ruler.
+- ``euclidian`` ``1`` for euclidian ruler, and ``0`` for regular ruler.
+
+To remove a single ruler:
+
+```
+gui::delete_ruler name
+```
+
+Options description: 
+- ``name`` name of the ruler.
+
+To remove all the rulers:
+
+```
+gui::clear_rulers
+```
+
+### Heat Maps
+
+The currently availble heat maps are:
+
+- ``Power``
+- ``Routing``
+- ``Placement``
+- ``IRDrop``
+- ``RUDY`` [^RUDY]
+
+To control the settings in the heat maps:
+
+```
+gui::set_heatmap name option
+gui::set_heatmap name option value
+```
+
+Options description:
+- ``name`` is the name of the heatmap.
+- ``option`` is the name of the option to modify. If option is ``rebuild`` the map will be destroyed and rebuilt.
+- ``value`` is the new value for the specified option. This is not used when rebuilding map.
+
+These options can also be modified in the GUI by double-clicking the underlined display control for the heat map.
+
+
+To save the raw data from the heat maps ins a comma separated value (CSV) format:
+
+```
+gui::dump_heatmap name filename
+```
+
+Options description: 
+- ``name`` is the name of the heatmap.
+- ``filename`` path to the file to write the data to.
+
+[^RUDY]: RUDY means Rectangular Uniform wire DensitY, which can predict the routing density very rough and quickly. You can see this notion in [this paper](https://past.date-conference.com/proceedings-archive/2007/DATE07/PDFFILES/08.7_1.PDF) 
+
+
+
+### GUI Display Controls
+
+Control the visible and selected elements in the layout:
+
+```
+gui::set_display_controls name display_type value
+```
+
+Options description: 
+- ``name`` is the name of the control. For example, for the power nets option this would be ``Signals/Power`` or could be ``Layers/*`` to set the option for all the layers.
+- ``display_type`` is either ``visible`` or ``selectable``
+- ``value`` is either ``true`` or ``false``
+
+To check the visibility or selectability of elements in the layout:
+
+```
+gui::check_display_controls name display_type 
+```
+
+Options description: 
+- ``name`` is the name of the control. For example, for the power nets option this would be ``Signals/Power`` or could be ``Layers/*`` to set the option for all the layers.
+- ``display_type`` is either ``visible`` or ``selectable``
+
+
+When performing a batch operation changing the display controls settings, the following commands can be used to save the current state of the display controls and restore them at the end.
+
+```
+gui::save_display_controls
+gui::restore_display_controls
+```
+
+### GUI Controls
+
+To request user input via the GUI:
+
+```
+gui::input_dialog title question
+```
+
+Returns: a string with the input, or empty string if canceled.
+
+Options description: 
+- ``title`` is the title of the input message box.
+- ``question`` is the text for the message box.
+
+Pause the execution of the script:
+
+```
+gui::pause 
+gui::pause timeout
+```
+
+Options description: 
+- ``timeout`` is specified in milliseconds, if it is not provided the pause will last until the user presses the Continue button.
+
+To open or close a specific layout widget:
+
+```
+gui::show_widget name
+gui::hide_widget name
+```
+
+Options description: 
+- ``name`` of the widget. For example, the display controls would be "Display Control".
+
+## License
+
+BSD 3-Clause License. See [LICENSE](../../LICENSE) file.

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@@ -0,0 +1,159 @@
+# Initialize Floorplan
+
+This tool initializes floorplan constraints, die/core area, and makes tracks. 
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Initialize Floorplan
+
+Do note that there are two ways of setting the floorplan dimensions.
+The user can either specify manually die/core area, or
+specify the utilization/aspect ratio.
+
+#### Method 1: Automatic die size calculation
+
+```
+initialize_floorplan
+  [-utilization util]
+  [-aspect_ratio ratio]
+  [-core_space space | {bottom top left right}]
+  [-sites site_name]
+```
+##### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-utilization` | Percentage utilization. Allowed values are `double` `>0`, more than 100% utilization can be useful with mock abstracts. |
+| `-aspect_ratio` | Ratio $\frac{height}{width}$. The default value is `1.0` and the allowed values are floats `[0, 1.0]`. |
+| `-core_space` | Space around the core, default `0.0` microns. Allowed values are either one value for all margins or a set of four values, one for each margin. The order of the four values are: `{bottom top left right}`. |
+| `-sites` | Tcl list of sites to make rows for (e.g. `{SITEXX, SITEYY}`) |
+
+
+#### Method 2: Set die/core area
+
+```tcl
+initialize_floorplan
+  [-die_area {llx lly urx ury}]
+  [-core_area {llx lly urx ury}]
+  [-additional_sites site_names]
+  -site site_name
+```
+
+##### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-die_area` | Die area coordinates in microns (lower left x/y and upper right x/y coordinates). |
+| `-core_area` | Core area coordinates in microns (lower left x/y and upper right x/y coordinates). |
+| `-site` | The LEF site to make rows for. |
+| `-additional_sites` | Any additional LEF site to make rows. |
+
+The die area and core area used to write ROWs can be specified explicitly
+with the `-die_area` and `-core_area` arguments. Alternatively, the die and
+core areas can be computed from the design size and utilization as shown below:
+
+The -site argument determines the basic single-height rows to make.
+For a hybrid row design the site should have a row pattern.  Any sites
+referenced by an instance in the netlist will also have rows
+constructed for them.
+
+Additional sites are specified if you wish to have rows for a site
+that is not used in the nelist but may be needed later.  For example,
+you might not have any double height cells in the incoming netlist but
+you expect some to be generated by flop clustering later in the flow.
+
+Example computation:
+
+```
+core_area = design_area / (utilization / 100)
+core_width = sqrt(core_area / aspect_ratio)
+core_height = core_width * aspect_ratio
+core = ( core_space_left, core_space_bottom )
+      ( core_space_left + core_width, core_space_bottom + core_height )
+die =  ( 0, 0 )
+      ( core_width + core_space_left + core_space_right,
+        core_height + core_space_bottom + core_space_top )
+```
+
+### Make Tracks
+
+The `initialize_floorplan` command removes existing tracks. 
+
+Use the `make_tracks` command to add routing tracks to a floorplan.
+
+```tcl
+make_tracks 
+    [layer]
+    [-x_pitch x_pitch]
+    [-y_pitch y_pitch]
+    [-x_offset x_offset]
+    [-y_offset y_offset]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `layer` | Select layer name to make tracks for. Defaults to all layers. |
+| `-x_pitch`, `-y_pitch` | If set, overrides the LEF technology x-/y- pitch. Use the same unit as in the LEF file. |
+| `-x_offset`, `-y_offset` | If set, overrides the LEF technology x-/y- offset. Use the same unit as in the LEFT file. |
+
+### Inserting tieoff cells
+
+To insert tiecells:
+
+```tcl
+insert_tiecells 
+    tie_pin
+    [-prefix inst_prefix]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `tie_pin` | Indicates the master and port to use to tie off nets. For example, `LOGIC0_X1/Z` for the Nangate45 library, where `LOGIC0_X1` is the master and `Z` is the output port on the master. |
+| `-prefix` | Used to control the prefix of the new tiecell names. This will default to `TIEOFF_`. |
+
+### Useful developer functions
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/InitFloorplan.cc) or the [swig file](./src/InitFloorPlan.i).
+
+| Command Name | Description |
+| ----- | ----- |
+| `microns_to_mfg_grid` | Convert microns to manufacturing grid DBU. |
+
+## Example scripts
+
+Example scripts on running `ifp` for a sample design of `mpd_top` are as follows:
+
+```tcl
+./test/upf_test.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out
+[GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+ifp+in%3Atitle)
+about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

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@@ -0,0 +1,151 @@
+# Hierarchical Macro Placement
+
+A hierarchical automatic macro placer for large-scale complex IP blocks, "Hier-RTLMP".
+This tool builds on the existing RTLMP (`mpl`) framework, adopting a multilevel physical 
+planning approach that exploits the hierarchy and data flow inherent in the design RTL.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Hier-RTLMP algorithm
+
+```tcl
+rtl_macro_placer 
+    [-max_num_macro max_num_macro]
+    [-min_num_macro min_num_macro]
+    [-max_num_inst max_num_inst]  
+    [-min_num_inst min_num_inst] 
+    [-tolerance tolerance]     
+    [-max_num_level max_num_level] 
+    [-coarsening_ratio coarsening_ratio]
+    [-num_bundled_ios num_bundled_ios]
+    [-large_net_threshold large_net_threshold]
+    [-signature_net_threshold signature_net_threshold]
+    [-halo_width halo_width] 
+    [-fence_lx fence_lx] 
+    [-fence_ly fence_ly]
+    [-fence_ux fence_ux]
+    [-fence_uy fence_uy]
+    [-area_weight area_weight] 
+    [-outline_weight outline_weight] 
+    [-wirelength_weight wirelength_weight]
+    [-guidance_weight guidance_weight]
+    [-fence_weight fence_weight] 
+    [-boundary_weight boundary_weight]
+    [-notch_weight notch_weight]
+    [-macro_blockage_weight macro_blockage_weight]
+    [-pin_access_th pin_access_th]
+    [-target_util target_util]
+    [-target_dead_space target_dead_space]
+    [-min_ar min_ar]
+    [-snap_layer snap_layer]
+    [-bus_planning]
+    [-report_directory report_directory]
+    [-write_macro_placement file_name]
+```
+
+#### Generic Parameters
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-max_num_macro`, `-min_num_macro` | Maximum/minimum number of macros in a cluster. The default value is `0` for both, and the allowed values are integers `[0, MAX_INT]`. |
+| `-max_num_inst`, `-min_num_inst` | Maximum/minimum number of standard cells in a cluster. The default value is `0` for both, and the allowed values are integers `[0, MAX_INT]`. |
+| `-tolerance` | Add a margin to the minimum and maximum number of macros/std cells in a cluster. For min, we multiply by (1 - `tol`), and for the max (1 + `tol`). This is to improve the robustness of hierarchical clustering. The allowed values are floats `[0, 1)`, and the default value is `0.1`. |
+| `-max_num_level` | Maximum depth of physical hierarchical tree. The default value is `2`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-coarsening_ratio` | The larger the coarsening_ratio, the faster the convergence process. The allowed values are floats, and the default value is `10.0`. |
+| `-num_bundled_ios` | Specifies the number of bundled pins for the left, right, top, and bottom boundaries. The default value is `3`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-large_net_threshold` | Ignore nets with many connections during clustering, such as global nets. The default value is `50`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-signature_net_threshold` | Minimum number of connections between two clusters to be identified as connected. The default value is `50`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-halo_width` | Horizontal/vertical halo around macros (microns). The allowed values are floats, and the default value is `0.0`. |
+| `-fence_lx`, `-fence_ly`, `-fence_ux`, `-fence_uy` | Defines the global fence bounding box coordinates. The default values are the core area coordinates). |
+| `-pin_access_th` | Specifies the pin access threshold value of macros. The default value is `0.0`, and the allowed values are floats [0,1]. |
+| `-target_util` | Specifies the target utilization of `MixedCluster` and has higher priority than target_dead_space. The allowed values are floats, and the default value is `0.25`. |
+| `-target_dead_space` | Specifies the target dead space percentage, which influences the utilization of `StandardCellCluster`. The allowed values are floats, and the default value is `0.05`. |
+| `-min_ar` | Specifies the minimum aspect ratio $a$, or the ratio of its width to height of a `StandardCellCluster` from $[a, \frac{1}{a}]$. The allowed values are floats, and the default value is `0.33`. |
+| `-snap_layer` | Snap macro origins to this routing layer track. The default value is 4, and the allowed values are integers `[1, MAX_LAYER]`). |
+| `-bus_planning` | Flag to enable bus planning. We recommend to enable bus planning for technologies with very limited routing layers such as SKY130 and GF180. As for technologies such as NanGate45 and ASAP7, we recommend to keep it disabled. |
+| `-report_directory` | Save reports to this directory. |
+| `-write_macro_placement` | Generates a file with the placement of the macros placed by HierRTLMP flow in the format of multiple calls for the `place_macro` command. |
+
+
+#### Simulated Annealing Weight parameters
+
+Do note that while action probabilities are normalized to 1.0, the weights are not necessarily normalized. 
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-area_weight` | Weight for the area of current floorplan.  The allowed values are floats, and the default value is `0.1`. |
+| `-outline_weight` | Weight for violating the fixed outline constraint, meaning that all clusters should be placed within the shape of their parent cluster.  The allowed values are floats, and the default value is `100.0`. |
+| `-wirelength_weight` | Weight for half-perimeter wirelength.  The allowed values are floats, and the default value is `100.0`. |
+| `-guidance_weight` | Weight for guidance cost or clusters being placed near specified regions if users provide such constraints.  The allowed values are floats, and the default value is `10.0`. |
+| `-fence_weight` | Weight for fence cost, or how far the macro is from zero fence violation.  The allowed values are floats, and the default value is `10.0`. |
+| `-boundary_weight` | Weight for the boundary, or how far the hard macro clusters are from boundaries. Note that mixed macro clusters are not pushed, thus not considered in this cost.  The allowed values are floats, and the default value is `50.0`. |
+| `-notch_weight` | Weight for the notch, or the existence of dead space that cannot be used for placement & routing. Note that this cost applies only to hard macro clusters.  The allowed values are floats, and the default value is `10.0`. |
+| `-macro_blockage_weight` | Weight for macro blockage, or the overlapping instances of the macro.  The allowed values are floats, and the default value is `10.0`. |
+
+### Write Macro Placement
+
+Command to generate a file with the placement of the macros in the design using multiple calls for the `place_macro` command:
+
+```tcl
+write_macro_placement file_name
+```
+
+### Place Macro
+
+Command for placement of one specific macro.
+
+```tcl
+place_macro
+    -macro_name macro_name
+    -location {x y}
+    [-orientation orientation]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-macro_name` | The name of a macro of the design. |
+| `-location` | The lower left corner of the macro in microns. |
+| `-orientation` | The orientation according to odb. If nothing is specified, defaults to `R0`.  We only allow `R0`, `MY`, `MX` and `R180`.  |
+
+## Example scripts
+
+Example of a script demonstrating how to run `mpl2` on a sample design of `bp_fe_top` as follows:
+
+```shell
+./test/bp_fe_top.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## References
+1. A. B. Kahng, R. Varadarajan and Z. Wang, 
+"RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement",
+[(.pdf)](https://vlsicad.ucsd.edu/Publications/Conferences/389/c389.pdf), Proc. ACM/IEEE Intl. Symp. on Physical Design, 2022, pp. 3-11.
+1. A. B. Kahng, R. Varadarajan and Z. Wang,
+"Hier-RTLMP: A hierarchical automatic macro placer for large-scale complex IP blocks.",
+[(.pdf)](https://arxiv.org/pdf/2304.11761.pdf), arXiv preprint arXiv:2304.11761, 2023.
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+hier-rtlmp+OR+hier+OR+mpl2) about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](../../LICENSE) file.

data/markdown/OR_userguide/OR_mpl_README.md

@@ -0,0 +1,86 @@
+# Macro Placement
+
+The macro placement module in OpenROAD (`mpl`) is based on 
+TritonMacroPlacer, an open-source ParquetFP-based macro cell placer.
+The macro placer places macros/blocks honoring halos, channels
+and cell row "snapping".
+Run `global_placement` before macro placement.
+
+Approximately $\Bigl\lceil [{\frac{numMacros}{3}}]^{1.5} \Bigr\rceil$ quadrisections
+of the initial placed mixed-size layout are explored and packed using
+ParquetFP-based annealing. The best resulting floorplan according to a
+heuristic evaluation function is kept.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Macro Placement
+
+```tcl
+macro_placement 
+    [-halo {halo_x halo_y}]
+    [-channel {channel_x channel_y}]
+    [-fence_region {lx ly ux uy}]
+    [-snap_layer snap_layer_number]
+    [-style corner_wax_wl|corner_min_wl]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-halo` | Horizontal and vertical halo around macros (microns). |
+| `-channel` | Horizontal and vertical channel width between macros (microns). |
+| `-fence_region` | Restrict macro placements to a region (microns). Defaults to the core area. |
+| `-snap_layer` | Snap macro origins to this routing layer track. |
+| `-style` | Placement style, to choose either `corner_max_wl` or `corner_min_wl`. The default value is `corner_max_wl`. |
+
+For placement style, `corner_max_wl` means that choosing the partitions that maximise the wirelength 
+of connections between the macros to force them to the corners. Vice versa for `corner_min_wl`.
+
+Macros will be placed with $max(halo * 2, channel)$ spacing between macros, and between
+macros and the fence/die boundary. If no solutions are found, try reducing the
+channel/halo.
+
+
+### Useful developer functions
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/MacroPlacer.cpp) or the [swig file](./src/MacroPlacer.i).
+
+| Command Name | Description |
+| ----- | ----- |
+| `macro_placement_debug` | Macro placement debugging. Note that GUI must be present for this command, otherwise a segfault will occur. | 
+
+## Example scripts
+
+Example scripts demonstrating how to run TritonMacroPlace on a sample design of `east_west` as follows:
+
+```tcl
+./test/east_west.tcl
+./test/east_west1.tcl
+./test/east_west2.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+mpl) about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](../../LICENSE) file.

data/markdown/OR_userguide/OR_odb_OR_codeGenerator_README.md

@@ -0,0 +1,11 @@
+# Automatic Code Generator
+
+This is an automatic code generation tool for OpenDB objects and Iterators. To test the tool you can use the following command
+
+``` shell
+python3 gen.py --json schema.json --src_dir ../db --include_dir ../../include/odb --templates templates
+```
+
+Where schema.json is the json file that includes the requirements, src is the source files directory, include is the include directory, and templates is the directory including the jinja templates for the classes.
+
+Empty sections are removed by default from the output.  If you need to add someting to a section that is currently empty, you can run the generator with --keep_empty to preserve them.  Once the section is filled in, the flag can be dropped and the code regnerated to remove the remaining empty sections.

data/markdown/OR_userguide/OR_odb_README.md

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+# OpenDB
+
+OpenDB is a design database to support tools for physical chip design. It
+was originally developed by Athena Design Systems. Nefelus, Inc. acquired
+the rights to the code and open-sourced it with BSD-3 license in 2019 to support the DARPA
+OpenROAD project.
+
+The structure of OpenDB is based on the text file formats LEF
+(library) and DEF (design) formats version 5.6.  OpenDB supports a
+binary file format to save and load the design much faster than using
+LEF and DEF.
+
+OpenDB is written in C++ 98 with standard library style iterators.
+The classes are designed to be fast enough to base an application on without
+having to copy them into application-specific structures.
+
+
+## Directory structure
+
+```
+include/odb/db.h - public header for all database classes
+src/db - private/internal database representations
+src/lefin - LEF reader
+src/lefout - LEF writer
+src/defin - DEF reader
+src/defout - DEF writer
+```
+
+## Database API
+
+We are still working on documenting the APIs.  We have over 1,800 objects
+and functions that we are still documenting (for both TCL and Python).
+**Contributions are very welcome in this effort**. Find starting points below.
+
+### TCL
+
+After building successfully, run OpenDB Tcl shell using
+`../../build/src/odb/src/swig/tcl/odbtcl`. An example usage:
+
+```
+set db [dbDatabase_create]
+set lef_parser [new_lefin $db true]
+set tech [lefin_createTech $lef_parser ./src/odb/test/data/gscl45nm.lef]
+```
+
+You can find examples on using the API from Tcl under `test/tcl/` directory.
+
+The full set of the Tcl commands exposed can be found under
+`./build/src/swig/tcl/opendb_wrapper.cpp`. Search for `SWIG_prefix`.
+
+
+### Python
+
+After building successfully, run `openroad -python` to enable the Python
+interpreter. You can find examples on using the API from Python under
+`test/python/` directory.
+
+To list the full set of the Python classes exposed run `openroad -python`
+then:
+```
+import openroad
+import odb
+print(', '.join(dir(openroad)))
+print(', '.join(dir(odb)))
+```
+
+### C++
+
+All public database classes are defined in `db.h`. These class definitions
+provide all functions for examining and modifying the database objects. The
+database is an object itself, so multiple database objects can exist
+simultaneously (no global state).
+
+`dbTypes.h` defines types returned by database class member functions.
+
+All database objects are in the `odb` namespace.
+
+-   `dbChip`
+-   `dbBlock`
+-   `dbTech`
+-   `dbLib`
+
+All database objects have a 32bit object identifier accessed with the
+`dbObject::getOID` base class member function that returns a `uint`. This
+identifier is preserved across save/restores of the database so it should
+be used to reference database object by data structures instead of pointers
+if the reference lifetime is across database save/restores. OIDs allow the
+database to have exactly the same layout across save/restores.
+
+The database distance units are **nanometers** and use the type `uint`.
+
+## Example scripts
+
+## Regression tests
+
+There are a set of regression tests in /test.
+
+```
+./test/regression-tcl.sh
+./test/regression-py.sh
+```
+
+## Database Internals
+
+The internal description included here is paraphrased from Lukas van Ginneken
+by James Cherry.
+
+The database separates the implementation from the interface, and as a result,
+each class becomes two classes, a public one and a private one. For instance,
+`dbInst` has the public API functions, while class `_dbInst` has the private
+data fields.
+
+The objects are allocated in dynamically resizable tables, the implementation
+of which is in `dbTable.hpp`. Each table consists of a number of pages,
+each containing 128 objects. The table contains the body of the `struct`,
+not a set of pointers. This eliminates most of the pointer overhead while
+iteration is accomplished by stepping through the table. Thus, grouping these
+objects does not require a doubly-linked list and saves 16 bytes per object
+(at the cost of some table overhead). Each object has an id, which is the
+index into the table. The lowest 7 bits are the index in the page, while
+the higher bits are the page number. Object id's are persistent when saving
+and reading the data model to disk, even as pointer addresses may change.
+
+Everything in the data model can be stored on disk and restored from disk
+exactly the way it was. An extensive set of equality tests and diff functions
+make it possible to check for even the smallest deviation. The capability
+to save an exact copy of the state of the system makes it possible to create
+a checkpoint. This is a necessary capability for debugging complex systems.
+
+The code follows the definition of LEF and DEF closely and reflects many of
+the idiosyncrasies of LEF and DEF. The code defines many types of objects
+to reflect LEF and DEF constructs although it sometimes uses different
+terminology, for instance, the object to represent a library cell is called
+`dbMaster` while the LEF keyword is MACRO.
+
+The data model supports the EEQ and LEQ keywords (i.e., electrically equivalent
+and logically equivalent Masters), which could be useful for sizing. However,
+it does not support any logic function representation. In general, there is
+very limited support for synthesis-specific information: no way to represent
+busses, no way to represent logic function, very limited understanding of
+signal flow, limited support of timing information, and no support for high
+level synthesis or test insertion.
+
+The db represents routing as in DEF, representing a trace from point to point
+with a given width. The layout for a net is stored in a class named `dbWire`
+and it requires a special `dbWireDecoder` (which works like an iterator)
+to unpack the data and another `dbWireEncoder` to pack it. The data model
+does not support a region query and objects that are in the same layer are
+scattered about the data model and are of different classes.
+
+This means that whatever tool is using the layout information will have to
+build its own data structures that are suitable to the layout operations
+of that tool. For instance, the router, the extractor, and the DRC engine
+would each have to build their unique data structures. This encourages
+batch mode operation (route the whole chip, extract the whole chip, run
+DRC on the whole chip).
+
+## Limitations
+
+## FAQs
+
+Check out
+[GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+fastroute+in%3Atitle)
+about this tool.
+
+
+## LICENSE
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_odb_doc_OpenDB-AddFieldsInDbObjects.md

@@ -0,0 +1,15 @@
+# Adding new fields in DB Object
+
+For example `add_pitchDiag` in object `DbTechLayer`.
+
+|   | Action                                                 | File              | Source Code                                                                        |
+|---|--------------------------------------------------------|-------------------|------------------------------------------------------------------------------------|
+| 1 | Add Fields at the .h file                              | `dbTechLayer.h`   |                                                                                    |
+| 2 | Define a keyword for db rev number                     | `dbDatabase.h`    | `#define ADS_DB_DF58 52`                                                           |
+| 3 | Set the current rev number same as                     | `dbDatabase.h`    | `#define ADS_DB_SCHEMA_MINOR 52`                                                   |
+| 4 | Stream in new fields Conditionally upon Schema number  | `dbTechLayer.cpp` | `if ( stream.getDatabase()->isSchema(ADS_DB_DF58) ) { stream >> layer._pitchDiag;` |
+| 5 | Stream out new fields Conditionally upon Schema number | `dbTechLayer.cpp` | `if ( stream.getDatabase()->isSchema(ADS_DB_DF58) ) { stream << layer._pitchDiag;` |
+| 6 | Conditionally Diff new fields                          | `dbTechLayer.cpp` | `if ( stream.getDatabase()->isSchema(ADS_DB_DF58) ) { DIFF_FIELD(_pitchDiag);`     |
+| 7 | Conditionally Diff Out new fields                      | `dbTechLayer.cpp` | `if ( stream.getDatabase()->isSchema(ADS_DB_DF58) ) { DIFF_OUT_FIELD(_pitchDiag);` |
+| 8 | Created access APIs to the fields                      | `dbTechLayer.cpp` | `"dbTechLayer::getPitchDiag(), dbTechLayer::setPitchDiag( int pitch )"`            |
+| 9 | Add new APIs in include/db.h                           | db.h              | `class dbTechLayer`                                                                |

data/markdown/OR_userguide/OR_odb_test_unitTestsPython_README.md

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+ # Python Unit Tests
+
+## Running tests
+
+For running the python unit tests you will need to install first *testtools* and *unittest-parallel* which enables concurrent unit testing
+
+``` shell
+pip3 install testtools
+pip3 install unittest-parallel
+```
+
+Then, you can run the unit tests  in sequence by running
+
+``` shell
+../unitTests.sh
+```
+
+or in parallel by running
+
+``` shell
+../unitTests.sh parallel
+```
+
+**Note**: The test cases within each Unit Test run in parallel in both situations
+
+--------------------------------------------------------------------------
+
+## <u>Tests Structure</u>
+
+The directory unitTestsPython includes unit tests for OpenDB Python APIs. Any test file starts with 'Test' followed by the test target.
+
+### odbUnitTest.py:
+
+This includes `TestCase` class which inherits from `unittest.TestCase` with additional functionalities:
+
+* `changeAndTest(self,obj,SetterName,GetterName,expectedVal,*args)`which is a function for changing a value and testing for the effect of that change where:
+
+  * `obj` is the object to be tested
+  * `SetterName` is the name of the function to be called for changing a value
+  * `GetterName` is the name of the function to be called for testing the effect
+  * `expectedVal` is the expected value for the testing
+  * `*args` are the arguments passed to the `SetterName` function
+
+  So, in the end, the expected behavior is:
+
+``` python
+obj.SetterName(*args)
+
+assert(obj.GetterName()==expectedVal)
+```
+
+
+* `check(self,obj,GetterName,expectedVal,*args)` which tests against expected value
+
+* `change(self,obj,SetterName,*args)` which changes a value in the object
+
+* `main()` runs the `TestCase` in sequential order
+
+* `mainParallel(Test)` runs the passed `Test` class in parallel
+
+### helper.py:
+
+A set of functions for creating simple db instances to be used for testing.  You can find the description of each function in the comments
+
+### TestNet.py:
+
+Unit test class for testing dbNet. It inherits from `odbUnitTest.TestCase` . it consists of
+
+* `setUp(self)` function to be called before each test case. Here, we create the database with the desired chip, block, masters, instances and nets.
+* `tearDown(self)` function to be called after each test case. Here, we destroy our db.
+* `test_*(self)` the test cases functions. Their names should start with `test` for the unittest suite to recognize.
+
+### TestDestroy.py:
+
+Integration test class for testing the `destroy(*args)` function on OpenDB.
+
+* `test_destroy_net` destroying net and testing for the effect on the *block,inst, iterms and bterms*
+* `test_destroy_inst` destroying instance and testing for the effect on *block, iterms, net, bterms*
+* `test_destroy_bterm` destroying bterm and testing for the effect on *block and net*
+* `test_destroy_block` destroying block and testing for the effect on *block(parent and child relation), and chip*
+* `test_destroy_bpin` destroying bpin and testing for the effect on *bterm*
+* `test_create_destroy_wire` destroying wire and test for the effect on *net*
+* `test_destroy_capnode` destroying capnode and test for the effect on *net(node and connected ccsegs)*
+* `test_destroy_ccseg` destroying ccseg and test for the effect on *node,block and net*
+
+* `test_destroy_lib` destroying lib and test for the effect on *db*
+
+* `test_destroy_obstruction` destroying obstruction and test for the effect on *block*
+* `test_create_regions` creating regions and test for the effect on *block and region(parent and child relation)*
+* `test_destroy_region_child` destroying _ and test for the effect on *block and region(parent)*
+
+* `test_destroy_region_parent` destroying _ and test for the effect on *block*
+
+### TestBlock.py:
+
+Unit Test for dbBlock
+
+* `test_find` testing the find function with *BTerm, Child, Inst, Net, ITerm, ExtCornerBlock, nonDefaultRule, Region*
+
+* Testing the ComputeBBox() function through the first call of getBBox:
+  * `test_bbox0` testing empty block box
+  * `test_bbox1` testing block box with Inst placed
+  * `test_bbox2` testing block box with Inst and BPin placed
+  * `test_bbox3` testing block box with Inst, BPin and Obstruction placed
+  * `test_bbox3` testing block box with Inst, BPin, Obstruction and SWire placed
+
+### TestBTerm.py:
+
+Unit Test for dbBTerm
+
+* `test_idle` testing for idle disconnected  `BTerm` behavior
+* `test_connect` testing connect function of `BTerm` on `BTerm` and `Net`
+* `test_disconnect` testing disconnect function of `BTerm` on `BTerm` and `Net`
+
+### TestInst.py:
+
+Unit Test for dbInst
+
+* `test_swap_master` testing swap master function
+
+### TestITerm.py:
+
+Unit Test for dbITerm
+
+* `test_idle` testing for disconnected ITerm without a net
+* `test_connection_from_iterm` testing the connect(ITerm,...) and disconnect functions of ITerm and their effect on ITerm and Net
+* `test_connection_from_inst` testing the connect(Inst,...) and disconnect functions of ITerm and their effect on ITerm and Net
+* Testing for getAvgXY() function
+  * `test_avgxy_R0` testing with default orientation R0
+  * `test_avgxy_R90` testing with different orientation R90 for transformation
+
+--------------------------
+
+#### Problems Found In Testing
+
+* multiple core dumps that leads to aborting the process:
+  * dbNet.get1st*()			(when nothing on top of the list)
+  * childRegion.getParent()       (after destroying the parent region)
+* Implementation of ComputeBBox() is flawed and needs to be reconsidered

data/markdown/OR_userguide/OR_pad_README.md

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+# Chip-level Connections
+
+The chip-level connections module in OpenROAD (`pad`) is based on the
+open-source tool ICeWall. In this utility, either place an IO ring around the
+boundary of the chip and connect with either wirebond pads or a bump array.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Placing Terminals
+
+In the case where the bond pads are integrated into the padcell, the IO terminals need to be placed.
+To place a terminals on the padring
+
+```tcl
+place_io_terminals
+    -allow_non_top_layer
+    inst_pins
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-allow_non_top_layer` | Allow the terminal to be placed below the top layer. |
+| `inst_pins` | Instance pins to place the terminals on. |
+
+#### Examples
+```
+place_io_terminals u_*/PAD
+place_io_terminals u_*/VDD
+```
+
+### Defining a Bump Array
+
+To define a bump array.
+
+```tcl
+make_io_bump_array 
+    -bump master
+    -origin {x y}
+    -rows rows
+    -columns columns
+    -pitch {x y}
+    [-prefix prefix]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-bump` | Name of the bump master. |
+| `-origin` | Origin of the array. |
+| `-rows` | Number of rows to create. |
+| `-columns` | Number of columns to create. |
+| `-pitch` | Pitch of the array. |
+| `-prefix` | Name prefix for the bump array. The default value is `BUMP_`. |
+Example usage:
+
+```tcl
+make_io_bump_array -bump BUMP -origin "200 200" -rows 14 -columns 14 -pitch "200 200"
+```
+
+### Removing Entire Bump Array
+
+To remove a bump array.
+
+```tcl
+remove_io_bump_array -bump master
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-bump` | Name of the bump master. |
+
+Example usage:
+
+```tcl
+remove_io_bump_array -bump BUMP
+```
+
+### Removing a Single Bump Instance
+
+To remove a single bump instance.
+
+```tcl
+remove_io_bump instance_name
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `instance_name` | Name of the bump. |
+
+### Assigning a Net to a Bump
+
+To assign a net to a bump.
+
+```tcl
+assign_io_bump 
+    -net net
+    [-terminal iterm]
+    [-dont_route]
+    instance
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-net` | Net to connect to. |
+| `-terminal` | Instance terminal to route to. |
+| `-dont_route` | Flag to indicate that this bump should not be routed, only perform assignment. |
+| `instance` | Name of the bump. |
+
+Example usage:
+
+```tcl
+assign_io_bump -net p_ddr_addr_9_o BUMP_6_0
+assign_io_bump -net p_ddr_addr_8_o BUMP_6_2
+assign_io_bump -net DVSS BUMP_6_4
+assign_io_bump -net DVDD BUMP_7_3
+assign_io_bump -net DVDD -terminal u_dvdd/DVDD BUMP_8_3
+assign_io_bump -net p_ddr_addr_7_o BUMP_7_1
+assign_io_bump -net p_ddr_addr_6_o BUMP_7_0
+```
+
+### Define IO Rows
+
+Define an IO site for the pads to be placed into.
+
+```tcl
+make_io_sites 
+    -horizontal_site site
+    -vertical_site site
+    -corner_site site
+    -offset offset
+    [-rotation_horizontal rotation]
+    [-rotation_vertical rotation]
+    [-rotation_corner rotation]
+    [-ring_index index]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-horizontal_site` | Name of the site for the horizontal pads (east and west). |
+| `-vertical_site` | Name of the site for the vertical pads (north and south). |
+| `-corner_site` | Name of the site for the corner cells. |
+| `-offset` | Offset from the die edge to place the rows. |
+| `-rotation_horizontal` | Rotation to apply to the horizontal sites to ensure pads are placed correctly. The default value is `R0`. |
+| `-rotation_vertical` | Rotation to apply to the vertical sites to ensure pads are placed correctly. The default value is `R0`. |
+| `-rotation_corner` | Rotation to apply to the corner sites to ensure pads are placed correctly. The default value is `R0`. |
+| `-ring_index` | Used to specify the index of the ring in case of multiple rings. |
+
+Example usage:
+
+```tcl
+make_io_sites -horizontal_site IOSITE_H -vertical_site IOSITE_V -corner_site IOSITE_C -offset 35
+make_io_sites -horizontal_site IOSITE_H -vertical_site IOSITE_V -corner_site IOSITE_C -offset 35 -rotation_horizontal R180
+```
+
+### Remove IO Rows
+
+When the padring is complete, the following command can remove the IO rows to avoid causing confusion with the other tools.
+
+```tcl
+remove_io_rows
+```
+
+### Placing Corners
+
+To place the corner cells
+
+```tcl
+place_corners 
+    master
+    [-ring_index index]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `master` | Name of the master for the corners. |
+| `-ring_index` | Used to specify the index of the ring in case of multiple rings. |
+
+Example usage:
+
+```tcl
+place_corners sky130_fd_io__corner_bus_overlay
+```
+
+### Placing Pads
+
+To place a pad into the pad ring.
+
+```tcl
+place_pad 
+    -row row_name
+    -location offset
+    -mirror
+    [-master master]
+    name
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-row` | Name of the row to place the pad into, examples include: `IO_NORTH`, `IO_SOUTH`, `IO_WEST`, `IO_EAST`, `IO_NORTH_0`, `IO_NORTH_1`. |
+| `-location` | Offset from the bottom left chip edge to place the pad at. |
+| `-mirror` | Specifies if the pad should be mirrored. |
+| `-master` | Name of the instance master if the instance needs to be created. |
+| `name` | Name of the instance. |
+
+Example usage:
+
+```tcl
+place_pad -row IO_SOUTH -location 280.0 {u_clk.u_in}
+place_pad -row IO_SOUTH -location 360.0 -mirror {u_reset.u_in}
+place_pad -master sky130_fd_io__top_ground_hvc_wpad -row IO_SOUTH -location 439.5 {u_vzz_0}
+place_pad -master sky130_fd_io__top_power_hvc_wpad -row IO_SOUTH -location 517.5 {u_v18_0}
+```
+
+### Placing IO Filler Cells
+
+To place the IO filler cells.
+
+```tcl
+place_io_fill 
+    -row row_name
+    [-permit_overlaps masters]
+    masters
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-row` | Name of the row to place the pad into, examples include: `IO_NORTH`, `IO_SOUTH`, `IO_WEST`, `IO_EAST`, `IO_NORTH_0`, `IO_NORTH_1`. |
+| `-permit_overlaps` | Names of the masters for the IO filler cells that allow for overlapping. |
+| `masters` | Names of the masters for the IO filler cells. |
+
+Example usage: 
+
+```tcl
+place_io_fill -row IO_NORTH s8iom0s8_com_bus_slice_10um s8iom0s8_com_bus_slice_5um s8iom0s8_com_bus_slice_1um
+place_io_fill -row IO_SOUTH s8iom0s8_com_bus_slice_10um s8iom0s8_com_bus_slice_5um s8iom0s8_com_bus_slice_1um
+place_io_fill -row IO_WEST s8iom0s8_com_bus_slice_10um s8iom0s8_com_bus_slice_5um s8iom0s8_com_bus_slice_1um
+place_io_fill -row IO_EAST s8iom0s8_com_bus_slice_10um s8iom0s8_com_bus_slice_5um s8iom0s8_com_bus_slice_1um
+```
+
+### Connecting Ring Signals
+
+Once the ring is complete, use the following command to connect the ring signals.
+
+```tcl
+connect_by_abutment
+```
+
+### Placing Wirebond Pads
+
+To place the wirebond pads over the IO cells.
+
+```tcl
+place_bondpad 
+    -bond master
+    [-offset {x y}]
+    [-rotation rotation]
+    io_instances
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-bond` | Name of the bondpad master. |
+| `-offset` | Offset to place the bondpad at with respect to the io instance. |
+| `-rotation` | Rotation of the bondpad. |
+| `io_instances` | Names of the instances to add bond pads to. |
+
+Example usage:
+
+```tcl
+place_bondpad -bond PAD IO_*
+```
+
+### Creating False IO Sites
+
+If the library does not contain sites for the IO cells, the following command can be used to add them.
+This should not be used unless the sites are not in the library.
+
+```tcl
+make_fake_io_site 
+    -name name
+    -width width
+    -height height
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-name` | Name of the site. |
+| `-width` | Width of the site (in microns). |
+| `-height` | Height of the site (in microns). |
+
+Example usage:
+
+```tcl
+make_fake_io_site -name IO_HSITE -width 1 -height 204
+make_fake_io_site -name IO_VSITE -width 1 -height 200
+make_fake_io_site -name IO_CSITE -width 200 -height 204
+```
+
+### Redistribution Layer Routing
+
+To route the RDL for the bump arrays.
+
+```tcl
+rdl_route 
+    -layer layer
+    [-bump_via access_via]
+    [-pad_via access_via]
+    [-width width]
+    [-spacing spacing]
+    [-turn_penalty penalty]
+    [-allow45]
+    nets
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-layer` | Layer to route on. |
+| `-bump_via` | Via to use to to connect the bump to the routing layer. |
+| `-pad_via` | Via to use to to connect the pad cell to the routing layer. |
+| `-width` | Width of the routing. Defaults to minimum width for each respective layer. |
+| `-spacing` | Spacing of the routing. Defaults to minimum spacing for each respective layer. |
+| `-turn_penalty` | Scaling factor to apply to discurage turning to allow for straighter routes. The default value is `2.0`, and the allowed values are floats. |
+| `-allow45` | Specifies that 45 degree routing is permitted. |
+| `nets` | Nets to route. |
+
+### Useful Developer Commands
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/ICeWall.cpp) or the [swig file](./src/pad.i).
+
+| Command Name | Description |
+| ----- | ----- |
+| `find_site` | Find site given site name. |
+| `find_master` | Find master given master name. |
+| `find_instance` | Find instance given instance name. |
+| `find_net` | Find net given net name. |
+| `assert_required` | Assert argument that is required for `cmd` |
+| `connect_iterm` | Connect instance terminals. Required inputs are: `inst_name`, `iterm_name`, `net_name`. |
+| `convert_tcl` | These functions read from $ICeWall::library parameters to generate a standalone Tcl script. |
+
+## Example Scripts
+
+Example scripts for running ICeWall functions can be found in `./test`.
+
+```tcl
+./test/assign_bumps.tcl
+./test/bump_array_make.tcl
+./test/bump_array_remove.tcl
+./test/bump_array_remove_single.tcl
+./test/connect_by_abutment.tcl
+./test/make_io_sites.tcl
+./test/place_bondpad.tcl
+./test/place_bondpad_stagger.tcl
+./test/place_pad.tcl
+./test/rdl_route.tcl
+./test/rdl_route_45.tcl
+./test/rdl_route_assignments.tcl
+```
+
+## Regression Tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+pad)
+about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](../../LICENSE) file.

data/markdown/OR_userguide/OR_par_README.md

@@ -0,0 +1,582 @@
+# Partition Manager
+
+The partitioning module (`par`) is based on TritonPart, an open-source 
+constraints-driven partitioner. `par` can be used 
+to partition a hypergraph or a gate-level netlist.
+
+## Highlights
+- Start of the art multiple-constraints driven partitioning “multi-tool”
+- Optimizes cost function based on user requirement
+- Permissive open-source license
+- Solves multi-way partitioning with following features:
+  - Multidimensional real-value weights on vertices and hyperedges
+  - Multilevel coarsening and refinement framework
+  - Fixed vertices constraint
+  - Timing-driven partitioning framework 
+  - Group constraint: Groups of vertices need to be in same block
+  - Embedding-aware partitioning
+  
+## Dependency
+
+We use Google OR-Tools as our ILP solver. 
+
+Our recommendation is to follow the OpenROAD [DependencyInstaller](../etc/DependencyInstaller.sh) for installation of this requirement.
+
+Alternatively, you may also install Google OR-Tools 
+following these [instructions](https://developers.google.com/optimization/install).
+
+```{warning}
+Due to a build issue, TritonPart is not supported for macOS. Stay tuned to this page for updates!
+```
+
+## Main Algorithm
+
+An overview of the TritonPart algorithm is shown below. It takes as inputs 
+- Hypergraph $H(V,E)$ in `.hgr` format.
+- Vertex weight $w_v \in \mathcal{R}_+^m$
+- Hyperedge weight $w_e \in \mathcal{R}_+^n$
+- Number of blocks $K$.
+- Imbalance factor $\epsilon$.
+- User-specified cost function $\phi$.
+
+There are five main steps in the main algorithm,
+mainly 1) constraints-driven coarsening,
+2) initial partitioning, 3) refinement, 4) cut-overlay clustering and
+partitioning (COCP), and 5) V-cycle refinement. The steps for the 
+timing-aware algorithm may be found in the next [section](#timing-aware-algorithm). 
+
+1. Constraints-Driven Coarsening
+
+The first step involves multilevel coarsening. Specifically, at each level,
+clusters of vertices are identified, and the merged and represented
+as a single vertex in the resulting coarser hypergraph. In this algorithm,
+the First-Choice scheme is used, which traverses the vertices in the 
+hypergraph according to a given ordering and merges pairs of vertices with
+high connectivity. The connectivity between a pair of vertices $(u,v)$
+is measured as follows:
+
+$$r(u, v) = \sum_{e\in \{I(v)\cap I(u)\}} \frac{\langle \alpha, w_e\rangle}{|e|-1}$$
+
+To efficiently manage multiple constraints, the following enhancements are 
+made to the coarsening scheme above:
+
+- **Fixed Vertex Constraint**: Fixed vertices that belong to the same partitioning block are merged into a single vertex. 
+- **Grouping Constraint**: Vertices that belong to the same group are merged into a single vertex.
+- **Embedding Constraint**: The embedding information is incorporated into the heavy-edge rating function. The new connectivity is updated as follows:
+
+$$\hat{r}(u, v) = r(u, v) + \rho\frac{1}{||X_u - X_v||_2}$$
+
+where $\rho$ is a normalization factor set to the average distance between two
+vertex embeddings. When vertices $v_1, ... , v_t$ are merged into a single
+vertex $v_{coarse}$, the corresponding vertex embedding $X_{v_{coarse}}$
+is defined as the *center of gravity* of $t$ vertices:
+
+$$X_{v_{coarse}} = \sum_{j=1}^{t} \frac{||w_{v_j}||}{M} X_{v_j},\ where\ M= \sum_{j=1}^t ||w_{v_j}|| $$
+
+- **Community Guidance**: Only vertices within the same community are
+  considered for merging.
+- **Tie-breaking mechanism**: If multiple neighbor pairs have the same rating
+  score, combine the lexicographically first unmatched vertex to break ties.
+
+2. Initial Partitioning
+
+After completing the coarsening process, an initial partitioning solution for
+the coarsest hypergraph $H_c$ is derived. Two sub-steps are involved in this:
+the best partitioning solution from random and VILE partitioning is chosen
+from $\eta = 50$ runs as a warm-start to the ILP-based partitioner. The
+optimization is based on only the cut size rather than the cost function
+$\phi$ to keep the runtime reasonable.
+
+3. Refinement
+
+After a feasible solution $H_{c_\xi}$ is obtained by initial partitioning,
+uncoarsening and move-based refinement is performed to improve the
+partitioning solution. Three refinement heuristics are applied in sequence:
+- **$K$-way pairwise FM (PM)**: This addresses multi-way partitioning
+  as concurrent bi-partitioning problems in a restricted version of K-way
+  Fiduccia–Mattheyses (FM) algorithm. First, $\lfloor K/2\rfloor $ pairs of
+  blocks are obtained, with refinement-specific vertex movements restricted
+  to associated paired blocks. Next, two-way FM is concurrently performed on
+  all the block pairs. finally, a new configuration of block pairs is computed
+  at the end of the PM.
+- **Direct $K$-way FM**: Using $K$ priority queues, for each block $V_i$,
+  establish a priority queue that stores the vertices that can be potentially
+  moved from the current block to block $V_i$. This queue is ordered according
+  to the gain of the vertices. Gain is defined as the reduction in cost
+  function from the movement of the vertex from the current block to $V_i$.
+  Next, after a vertex move, each priority queue is updated independently, thus
+  enabling parallel updates via multi-threading. Next, early-stop is implemented
+  by limiting the maximum number of vertices moved to 100 per pass. Finally,
+  the *corking effect* is mitigated by traversing the priority queue belonging
+  to the vertex with the highest gain and identifying a feasible vertex move.
+- **Greedy Hyperedge Refinement (HER)**: First, randomly visit all
+  hyperedges. For each hyperedge $e$ that crosses the partition boundary,
+  determine whether a subset of vertices in $e$ can be moved without violating
+  the multi-dimensional balance constraints. The objective is to make $e$
+  entirely constrained in a block.
+
+4. Cut-Overlay Clustering and Partitioning (COCP)
+
+Cut-overlay Clustering and Partitioning (COCP) is a mechanism to
+combine multiple good-quality partitioning solutions to generate an
+improved solution. To begin, the sets of hyperedges cut in the $\theta$
+candidate solutions are denoted as $E_1,..., E_\theta \subset E$.  First,
+$\cup_{i=1}^\theta E_i$ is removed from the hypergraph $H(V, E)$, resulting in
+a number of connected components. Next, all vertices within each connected
+component are merged to form a coarser hypergraph $H_{overlay}$. If the
+number of vertices in $H_{overlay}$ is less than $thr_{ilp}$, ILP-based
+partitioning is performed. If not, a single round of constraints-driven
+coarsening is conducted to further reduce the size of $H_{overlay}$
+and generate a coarser hypergraph $H_{overlay}^{'}$. Finally, multilevel
+refinement is performed to further improve the partitioning solution at
+each level of the hierarchy and return the improved solution $S^{'}$.
+
+5. V-Cycle Refinement
+
+Cut-overlay clustering and partitioning produces a high-quality partitioning
+solution $S^{'}$. To improve it, there are three phases similar to *hMETIS*,
+namely multilevel coarsening, ILP-based partitioning, and refinement.
+Firstly, in multilevel partitioning, $S^{'}$ is used as a community guidance
+for the constraints-driven coarsening. Only vertices within the same block
+are permitted to be merged to ensure that the current solution $S^{'}$
+is preserved in the coarsest hypergraph $H_{c_\xi}$. In the ILP-based
+partitioning phase, if the number of vertices in $H_{c_\xi}$ does not exceed
+$thr_{ilp}$, run ILP-based partitioning to improve $S^{'}$. Otherwise,
+continue with $S^{'}$ in successive iterations of these two steps (default
+set to 2). The refinement phase is conducted as per step 3.
+
+![](./doc/algo.webp)<center>TritonPart algorithm at a glance</center>
+
+## Timing Aware Algorithm
+
+`par` can also be used as a timing-aware partitioning framework. A slack
+propagation methodology is used that optimizes cuts for both timing-critical
+and timing-noncritical paths.
+
+1. Extraction of Timing Paths and Slack Information
+
+First, the top $P$ timing-critical paths and the slack information of each
+hyperedge using the wireload model (WLM) is obtained from *OpenSTA*. The
+timing cost of each path is then calculated:
+
+$$t_p = (1- \frac{slack_p - \Delta}{clock\_period})^\mu$$
+
+where a fixed extra delay $\Delta$ is introduced for timing guardband,
+and $\mu$ (default 2) is the exponent.
+
+The snaking factor of a path $SF(p)$ is defined as the maximum number
+of block reentries along the path $p$. The timing cost of a hyperedge is
+computed using the timing weight corresponding to hyperedge slack $slack_e$
+and the accumulated timing cost of all paths traversing the hyperedge.
+
+$$t_e = (1- \frac{slack_e -\Delta}{clock\_period})^\mu + \sum_{\{p|e\in p\}}t_p$$
+
+2. Timing-aware Coarsening
+
+The timing-aware feature is achieved by adding a timing cost of hyperedge
+$t_e$ to the connectivity score earlier mentioned. If vertices $(u,v)$
+are associated with multiple critical paths, then they are more likely to
+be merged. This is reflected in the update score function:
+
+$$r_t(u,v) = \hat{r}(u,v) + \sum_{e\in\{I(v) \cap I(u)\}} \frac{\beta t_e}{|e| - 1}$$
+
+3. Timing-aware Refinement
+
+Timing-aware refinement is based on a similar cost function as the main
+algorithm. Instead, an additional slack propagation step is performed at
+the end of each PM/FM/HER pass.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Partition Netlist
+
+```tcl
+triton_part_hypergraph
+    -hypergraph_file hypergraph_file  
+    -num_parts num_parts  
+    -balance_constraint balance_constraint 
+    [-base_balance base_balance]
+    [-seed seed] 
+    [-vertex_dimension vertex_dimension] 
+    [-hyperedge_dimension hyperedge_dimension] 
+    [-placement_dimension placement_dimension] 
+    [-fixed_file fixed_file] 
+    [-community_file community_file] 
+    [-group_file group_file] 
+    [-placement_file placement_file] 
+    [-e_wt_factors e_wt_factors] 
+    [-v_wt_factors <v_wt_factors>] 
+    [-placement_wt_factors <placement_wt_factors>]
+    [-thr_coarsen_hyperedge_size_skip thr_coarsen_hyperedge_size_skip] 
+    [-thr_coarsen_vertices thr_coarsen_vertices] 
+    [-thr_coarsen_hyperedges thr_coarsen_hyperedges] 
+    [-coarsening_ratio coarsening_ratio] 
+    [-max_coarsen_iters max_coarsen_iters] 
+    [-adj_diff_ratio adj_diff_ratio] 
+    [-min_num_vertices_each_part min_num_vertices_each_part] 
+    [-num_initial_solutions num_initial_solutions] 
+    [-num_best_initial_solutions num_best_initial_solutions] 
+    [-refiner_iters refiner_iters] 
+    [-max_moves max_moves] 
+    [-early_stop_ratio early_stop_ratio] 
+    [-total_corking_passes total_corking_passes] 
+    [-v_cycle_flag v_cycle_flag ] 
+    [-max_num_vcycle max_num_vcycle] 
+    [-num_coarsen_solutions num_coarsen_solutions] 
+    [-num_vertices_threshold_ilp num_vertices_threshold_ilp] 
+    [-global_net_threshold global_net_threshold] 
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-num_parts` | Number of partitions. The default value is `2`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-balance_constraint` | Allowed imbalance between blocks. The default value is `1.0`, and the allowed values are floats. |
+| `-base_balance` | Tcl list of baseline imbalance between partitions. The default value is `{1.0}`, and the allowed values are floats that sum up to `1.0`. |
+| `-seed` | Random seed. The default value is `0`, and the allowed values are integers `[-MAX_INT, MAX_INT]`. |
+| `-vertex_dimension` | Number of vertices in the hypergraph. The default value is `1`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-hyperedge_dimension` | Number of hyperedges in hypergraph. The default value is `1`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-placement_dimension` | Number of dimensions for canvas if placement information is provided. The default value is `0`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-hypergraph_file` | Path to hypergraph file. |
+| `-fixed_file` | Path to fixed vertices constraint file. |
+| `-community_file` | Path to `community` attributes file to guide the partitioning process. |
+| `-group_file` | Path to `stay together` attributes file. |
+| `-placement_file` | Placement information file, each line corresponds to a group fixed vertices, community, and placement attributes following the [hMETIS](https://course.ece.cmu.edu/~ee760/760docs/hMetisManual.pdf) format. |
+| `-e_wt_factors` | Hyperedge weight factor. |
+| `-v_wt_factors` | Vertex weight factors. |
+| `-placement_wt_factors` | Placement weight factors. |
+| `-thr_coarsen_hyperedge_size_skip` | Threshold for ignoring large hyperedge (default 200, integer). |
+| `-thr_coarsen_vertices` | Number of vertices of coarsest hypergraph (default 10, integer). |
+| `-thr_coarsen_hyperedges` | Number of vertices of coarsest hypergraph (default 50, integer). |
+| `-coarsening_ratio` | Coarsening ratio of two adjacent hypergraphs (default 1.6, float). |
+| `-max_coarsen_iters` | Number of iterations (default 30, integer). |
+| `-adj_diff_ratio` | Minimum difference of two adjacent hypergraphs (default 0.0001, float). |
+| `-min_num_vertices_each_part` | Minimum number of vertices in each partition (default 4, integer). |
+| `-num_initial_solutions` | Number of initial solutions (default 50, integer). |
+| `-num_best_initial_solutions` | Number of top initial solutions to filter out (default 10, integer). |
+| `-refiner_iters` | Refinement iterations (default 10, integer). |
+| `-max_moves` | The allowed moves for each Fiduccia-Mattheyes (FM) algorithm pass or greedy refinement (default 60, integer). |
+| `-early_stop_ratio` | Describes the ratio $e$ where if the $n_{moved vertices} > n_{vertices} * e$, the tool exits the current FM pass. The intention behind this is that most of the gains are achieved by the first few FM moves. (default 0.5, float). |
+| `-total_corking_passes` | Maximum level of traversing the buckets to solve the "corking effect" (default 25, integer). |
+| `-v_cycle_flag` | Disables v-cycle is used to refine partitions (default true, bool). |
+| `-max_num_vcycle` | Maximum number of `vcycles` (default 1, integer). |
+| `-num_coarsen_solutions` | Number of coarsening solutions with different randoms seed (default 3, integer). |
+| `-num_vertices_threshold_ilp` | Describes threshold $t$, the number of vertices used for integer linear programming (ILP) partitioning. if $n_{vertices} > t$, do not use ILP-based partitioning.(default 50, integer). |
+| `-global_net_threshold` | If the net is larger than this, it will be ignored by TritonPart (default 1000, integer). |
+
+### Evaluate Hypergraph Partition
+
+```tcl
+evaluate_hypergraph_solution
+  -num_parts num_parts
+  -balance_constraint balance_constraint
+  -hypergraph_file hypergraph_file
+  -solution_file solution_file
+  [-base_balance base_balance]
+  [-vertex_dimension vertex_dimension]
+  [-hyperedge_dimension hyperedge_dimension]
+  [-fixed_file fixed_file]
+  [-group_file group_file]
+  [-e_wt_factors e_wt_factors]
+  [-v_wt_factors v_wt_factors] 
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-num_parts` | Number of partitions. The default value is `2`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-balance_constraint` | Allowed imbalance between blocks. The default value is `1.0`, and the allowed values are floats. |
+| `-vertex_dimension` | Number of vertices in the hypergraph. The default value is `1`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-hyperedge_dimension` | Number of hyperedges in hypergraph. The default value is `1`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-hypergraph_file` | Path to hypergraph file. |
+| `-solution_file` | Path to solution file. |
+| `-base_balance` | Tcl list of baseline imbalance between partitions. The default value is `{1.0}`, and the allowed values are floats that sum up to `1.0`. |
+| `-fixed_file` | Path to fixed vertices constraint file. |
+| `-group_file` | Path to `stay together` attributes file. |
+| `-e_wt_factors` | Hyperedge weight factor. |
+| `-v_wt_factors` | Vertex weight factor. |
+
+
+### Partition Netlist 
+
+```tcl
+triton_part_design
+    [-num_parts num_parts]
+    [-balance_constraint balance_constraint]
+    [-base_balance base_balance]
+    [-seed seed]
+    [-timing_aware_flag timing_aware_flag]
+    [-top_n top_n]
+    [-placement_flag placement_flag]
+    [-fence_flag fence_flag]
+    [-fence_lx fence_lx]
+    [-fence_ly fence_ly]
+    [-fence_ux fence_ux]
+    [-fence_uy fence_uy]
+    [-fixed_file fixed_file]
+    [-community_file community_file]
+    [-group_file group_file]
+    [-solution_file solution_file]
+    [-net_timing_factor net_timing_factor]
+    [-path_timing_factor path_timing_factor]
+    [-path_snaking_factor path_snaking_factor]
+    [-timing_exp_factor timing_exp_factor]
+    [-extra_delay extra_delay]
+    [-guardband_flag guardband_flag]
+    [-e_wt_factors e_wt_factors]
+    [-v_wt_factors v_wt_factors]
+    [-placement_wt_factors placement_wt_factors]
+    [-thr_coarsen_hyperedge_size_skip thr_coarsen_hyperedge_size_skip]
+    [-thr_coarsen_vertices thr_coarsen_vertices]
+    [-thr_coarsen_hyperedges thr_coarsen_hyperedges]
+    [-coarsening_ratio coarsening_ratio]
+    [-max_coarsen_iters max_coarsen_iters]
+    [-adj_diff_ratio adj_diff_ratio]
+    [-min_num_vertices_each_part min_num_vertices_each_part]
+    [-num_initial_solutions num_initial_solutions]
+    [-num_best_initial_solutions num_best_initial_solutions]
+    [-refiner_iters refiner_iters]
+    [-max_moves max_moves]
+    [-early_stop_ratio early_stop_ratio]
+    [-total_corking_passes total_corking_passes]
+    [-v_cycle_flag v_cycle_flag ]
+    [-max_num_vcycle max_num_vcycle]
+    [-num_coarsen_solutions num_coarsen_solutions]
+    [-num_vertices_threshold_ilp num_vertices_threshold_ilp]
+    [-global_net_threshold global_net_threshold]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-num_parts` | Number of partitions. The default value is `2`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-balance_constraint` | Allowed imbalance between blocks. The default value is `1.0`, and the allowed values are floats. |
+| `-base_balance` | Tcl list of baseline imbalance between partitions. The default value is `{1.0}`, and the allowed values are floats that sum up to `1.0`. |
+| `-seed` | Random seed. The default value is `1`, and the allowed values are integers `[-MAX_INT, MAX_INT]`. |
+| `-timing_aware_flag` | Enable timing-driven mode. The default value is `true`, and the allowed values are booleans. |
+| `-top_n` | Extract the top n critical timing paths. The default value is `1000`, and the allowed values are integers `[0, MAX_INT`. |
+| `-placement_flag` | Enable placement driven partitioning. The default value is `false`, and the allowed values are booleans. |
+| `-fence_flag ` | Consider fences in the partitioning. The default value is `false`, and the allowed values are booleans. |
+| `-fence_lx ` | Fence lower left x in microns. The default value is `0.0`, and the allowed values are floats. |
+| `-fence_ly ` | Fence lower left y in microns. The default value is `0.0`, and the allowed values are floats. |
+| `-fence_ux ` | Fence upper right x in microns. The default value is `0.0`, and the allowed values are floats. |
+| `-fence_uy ` | Fence upper right y in microns. The default value is `0.0`, and the allowed values are floats. |
+| `-fixed_file` | Path to fixed vertices constraint file |
+| `-community_file` | Path to `community` attributes file to guide the partitioning process. |
+| `-group_file` | Path to `stay together` attributes file. |
+| `-solution_file` | Path to solution file. |
+| `-net_timing_factor` | Hyperedge timing weight factor (default 1.0, float). |
+| `-path_timing_factor` | Cutting critical timing path weight factor (default 1.0, float). |
+| `-path_snaking_factor` | Snaking a critical path weight factor (default 1.0, float). |
+| `-timing_exp_factor` | Timing exponential factor for normalized slack (default 1.0, float). |
+| `-extra_delay` | Extra delay introduced by a cut (default 1e-9, float). |
+| `-guardband_flag` | Enable timing guardband option (default false, bool). |
+| `-e_wt_factors` | Hyperedge weight factor. |
+| `-v_wt_factors` | Vertex weight factor. |
+| `-placement_wt_factors` | Placement weight factor. |
+| `-thr_coarsen_hyperedge_size_skip` | Threshold for ignoring large hyperedge. The default value is `1000`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-thr_coarsen_vertices` | Number of vertices of coarsest hypergraph. The default value is `10`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-thr_coarsen_hyperedges` | Number of vertices of the coarsest hypergraph. The default value is `50`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-coarsening_ratio` | Coarsening ratio of two adjacent hypergraphs. The default value is `1.5`, and the allowed values are floats. |
+| `-max_coarsen_iters` | Number of iterations. The default value is `30`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-adj_diff_ratio` | Minimum ratio difference of two adjacent hypergraphs. The default value is `0.0001`, and the allowed values are floats. |
+| `-min_num_vertices_each_part` | Minimum number of vertices in each partition. The default value is `4`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-num_initial_solutions` | Number of initial solutions. The default value is `100`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-num_best_initial_solutions` | Number of top initial solutions to filter out. The default value is `10`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-refiner_iters` | Refinement iterations. The default value is `10`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-max_moves` | The allowed moves for each Fiduccia-Mattheyes (FM) algorithm pass or greedy refinement. The default value is `100`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-early_stop_ratio` | Describes the ratio $e$ where if the $n_{moved vertices} > n_{vertices} * e$, the tool exists the current FM pass. The intention behind this is that most of the gains are achieved by the first few FM moves. The default value is `0.5`, and the allowed values are floats. |
+| `-total_corking_passes` | Maximum level of traversing the buckets to solve the "corking effect". The default value is `25`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-v_cycle_flag` | Disables v-cycle is used to refine partitions. The default value is `true`, and the allowed values are booleans. |
+| `-max_num_vcycle` | Maximum number of vcycles. The default value is `1`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-num_coarsen_solutions` | Number of coarsening solutions with different randoms seed. The default value is `4`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-num_vertices_threshold_ilp` | Describes threshold $t$, the number of vertices used for integer linear programming (ILP) partitioning. if $n_{vertices} > t$, do not use ILP-based partitioning. The default value is `50`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-global_net_threshold` | If the net is larger than this, it will be ignored by TritonPart. The default value is `1000`, and the allowed values are integers `[0, MAX_INT]`. |
+
+### Evaluation Netlist Partition
+
+```tcl
+evaluate_part_design_solution
+    [-num_parts num_parts]
+    [-balance_constraint balance_constraint]
+    [-base_balance base_balance]
+    [-timing_aware_flag timing_aware_flag]
+    [-top_n top_n]
+    [-fence_flag fence_flag]
+    [-fence_lx fence_lx]
+    [-fence_ly fence_ly]
+    [-fence_ux fence_ux]
+    [-fence_uy fence_uy]
+    [-fixed_file fixed_file]
+    [-community_file community_file]
+    [-group_file group_file]
+    [-hypergraph_file hypergraph_file]
+    [-hypergraph_int_weight_file hypergraph_int_weight_file]
+    [-solution_file solution_file]
+    [-net_timing_factor net_timing_factor]
+    [-path_timing_factor path_timing_factor]
+    [-path_snaking_factor path_snaking_factor]
+    [-timing_exp_factor timing_exp_factor]
+    [-extra_delay extra_delay]
+    [-guardband_flag guardband_flag]
+    [-e_wt_factors e_wt_factors]
+    [-v_wt_factors v_wt_factors]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-num_parts` | Number of partitions. The default value is `2`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-balance_constraint` | Allowed imbalance between blocks. The default value is `1.0`, and the allowed values are floats. |
+| `-base_balance` | Tcl list of baseline imbalance between partitions. The default value is `{1.0}`, and the allowed values are floats that sum up to `1.0`. |
+| `-timing_aware_flag` | Enable timing-driven mode. The default value is `true`, and the allowed values are booleans. |
+| `-top_n` | Extract the top n critical timing paths. The default value is `1000`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-fence_flag ` | Consider fences in the partitioning. The default value is `false`, and the allowed values are booleans. |
+| `-fence_lx ` | Fence lower left x in microns. The default value is `0.0`, and the allowed values are floats. |
+| `-fence_ly ` | Fence lower left y in microns. The default value is `0.0`, and the allowed values are floats. |
+| `-fence_ux ` | Fence upper right x in microns. The default value is `0.0`, and the allowed values are floats. |
+| `-fence_uy ` | Fence upper right y in microns. The default value is `0.0`, and the allowed values are floats. | 
+| `-fixed_file` | Path to fixed vertices constraint file. |
+| `-community_file` | Path to `community` attributes file to guide the partitioning process. |
+| `-group_file` | Path to `stay together` attributes file. |
+| `-hypergraph_file` | Path to hypergraph file. |
+| `-hypergraph_int_weight_file` | Path to `hMETIS` format integer weight file. |
+| `-solution_file` | Path to solution file. |
+| `-net_timing_factor` | Hyperedge timing weight factor. The default value is `1.0`, and the allowed values are floats. |
+| `-path_timing_factor` | Cutting critical timing path weight factor. The default value is `1.0`, and the allowed values are floats. |
+| `-path_snaking_factor` | Snaking a critical path weight factor. The default value is `1.0`, and the allowed values are floats. |
+| `-timing_exp_factor` | Timing exponential factor for normalized slack. The default value is `1.0`, and the allowed values are floats. |
+| `-extra_delay` | Extra delay introduced by a cut. The default value is `1e-9`, and the allowed values are floats. |
+| `-guardband_flag` | Enable timing guardband option. The default value is 1`false`, and the allowed values are booleans. |
+| `-e_wt_factors` | Hyperedge weight factors. |
+| `-v_wt_factors` | Vertex weight factors. |
+
+### Write Partition to Verilog
+
+```tcl
+write_partition_verilog
+    [-port_prefix prefix]
+    [-module_suffix suffix]
+    [file]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-port_prefix` | Port name prefix. |
+| `-module_suffix` | Module name suffix. |
+| `file` | Filename to write partition verilog to. |
+
+### Read the Partition file
+
+```tcl
+read_partitioning
+    -read_file name
+    [-instance_map_file file_path]
+
+
+## Example Scripts
+
+### How to partition a hypergraph in the way you would using hMETIS (min-cut partitioning)
+
+```tcl
+triton_part_hypergraph -hypergraph_file des90.hgr -num_parts 5 -balance_constraint 2 -seed 2
+```
+You can also check the provided example [here](./examples/min-cut-partitioning/run_openroad.tcl).
+
+### How to perform the embedding-aware partitioning
+
+```tcl
+set num_parts 2
+set balance_constraint 2
+set seed 0
+set design sparcT1_chip2
+set hypergraph_file "${design}.hgr"
+set placement_file "${design}.hgr.ubfactor.2.numparts.2.embedding.dat"
+set solution_file "${design}.hgr.part.${num_parts}"
+
+triton_part_hypergraph  -hypergraph_file $hypergraph_file -num_parts $num_parts \
+                        -balance_constraint $balance_constraint \
+                        -seed $seed  \
+                        -placement_file ${placement_file} -placement_wt_factors { 0.00005 0.00005 } \
+                        -placement_dimension 2
+
+```
+
+You can find the provided example [here](./examples/embedding-aware-partitioning/run_placement_aware_flow.tcl).
+
+
+### How to partition a netlist
+
+```tcl
+# set technology information
+set ALL_LEFS “list_of_lefs”
+set ALL_LIBS “list_of_libs”
+# set design information
+set design “design_name”
+set top_design “top_design”
+set netlist “netlist.v”
+set sdc “timing.sdc”
+foreach lef_file ${ALL_LEFS} {
+  read_lef $lef_file
+}
+foreach lib_file ${ALL_LIBS} {
+  read_lib $lib_file
+}
+read_verilog $netlist
+link_design $top_design
+read_sdc $sdc
+
+set num_parts 5
+set balance_constraint 2
+set seed 0
+set top_n 100000
+# set the extra_delay_cut to 20% of the clock period
+# the extra_delay_cut is introduced for each cut hyperedge
+set extra_delay_cut 9.2e-10  
+set timing_aware_flag true
+set timing_guardband true
+set part_design_solution_file "${design}_part_design.hgr.part.${num_parts}"
+
+##############################################################################################
+### TritonPart with slack progagation
+##############################################################################################
+puts "Start TritonPart with slack propagation"
+# call triton_part to partition the netlist
+triton_part_design -num_parts $num_parts -balance_constraint $balance_constraint \
+                   -seed $seed -top_n $top_n \
+                   -timing_aware_flag $timing_aware_flag -extra_delay $extra_delay_cut \
+                   -guardband_flag $timing_guardband \
+                   -solution_file $part_design_solution_file 
+```
+
+You can find the provided example [here](./examples/timing-aware-partitioning/run_timing_aware_flow.tcl).
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests). 
+
+Simply run the following script: 
+
+```shell
+./test/regression
+```
+
+## References
+1. Bustany, I., Kahng, A. B., Koutis, I., Pramanik, B., & Wang, Z. (2023). K-SpecPart: A Supervised Spectral Framework for Multi-Way Hypergraph Partitioning Solution Improvement. arXiv preprint arXiv:2305.06167. [(.pdf)](https://arxiv.org/pdf/2305.06167)
+1. Bustany, I., Gasparyan, G., Kahng, A. B., Koutis, I., Pramanik, B., & Wang, Z. (2023). "An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design", Proc. ACM/IEEE International Conference of Computer-Aided Design 2023,[(.pdf)](https://vlsicad.ucsd.edu/Publications/Conferences/401/c401.pdf).
+
+
+## License
+
+BSD 3-Clause License. See [LICENSE](../../LICENSE) file.

data/markdown/OR_userguide/OR_pdn_README.md

@@ -0,0 +1,493 @@
+# Power Distribution Network Generator
+
+The power distribution network (PDN) generator module in OpenROAD (`pdn`) 
+is based on the PDNGEN tool. 
+This utility aims to simplify the process of adding a power grid into a
+floorplan. The aim is to specify a small set of power grid policies to be
+applied to the design, such as layers to use, stripe width and spacing,
+then have the utility generate the actual metal straps. Grid policies can
+be defined over the stdcell area, and over areas occupied by macros.
+
+```{seealso}
+To work with UPF files, refer to [Read UPF Utility](../upf/README.md).
+```
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Build Power Grid
+
+Build a power grid in accordance with the information specified.
+
+```tcl
+pdngen 
+    [-skip_trim]
+    [-dont_add_pins]
+    [-reset]
+    [-ripup]
+    [-report_only]
+    [-failed_via_report file]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-skip_trim` | Skip the metal trim step, which attempts to remove metal stubs. |
+| `-dont_add_pins` | Prevent the creation of block pins. |
+| `-reset` | Reset the grid and domain specifications. |
+| `-ripup` | Ripup the existing power grid, as specified by the voltage domains. |
+| `-report_only` | Print the current specifications. |
+| `-failed_via_report` | Generate a report file that can be viewed in the DRC viewer for all the failed vias (i.e., those that did not get built or were removed). |
+
+### Define Voltage Domains
+
+Defines a named voltage domain with the names of the power and ground nets for a region.
+
+This region must already exist in the floorplan before referencing it with the `set_voltage_domain` command. If the `-region` argument is not supplied, then the region is the entire core area of the design.
+
+```tcl
+set_voltage_domain 
+    -name domain_name
+    -power power_net_name 
+    -ground ground_net_name
+    [-region region_name]
+    [-secondary_power secondary_power_net] 
+    [-switched_power switched_power_net]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-name` | Defines the name of the voltage domain. The default is "Core" or region name if provided. |
+| `-power` | Specifies the name of the power net for this voltage domain. |
+| `-ground` | Specifies the name of the ground net for this voltage domain. |
+| `-region` | Specifies a region of the design occupied by this voltage domain. |
+| `-secondary_power` | Specifies the name of the secondary power net for this voltage domain. |
+| `-switched_power` | Specifies the name of the switched power net for switched power domains. |
+
+Example usage:
+
+```tcl
+set_voltage_domain -power VDD -ground VSS
+set_voltage_domain -name TEMP_ANALOG -region TEMP_ANALOG -power VIN -ground VSS
+set_voltage_domain -region test_domain -power VDD -ground VSS -secondary_power VREG
+```
+
+### Define Power Grid (General)
+
+Define the rules to describe a power grid pattern to be placed in the design.
+
+```{warning}
+`define_pdn_grid` is overloaded with two different signatures. Take note of the arguments when using this function!
+```
+
+```tcl
+define_pdn_grid 
+    [-name name] 
+    [-voltage_domain list_of_domain_names] 
+    [-pins list_of_pin_layers] 
+    [-starts_with POWER|GROUND] 
+    [-starts_with POWER|GROUND] 
+    [-obstructions list_of_layers]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-name` | The name to use when referring to this grid definition. |
+| `-voltage_domain` | This grid's voltage domain name. Defaults to the last domain created. |
+| `-pins` | List of layers where the power straps will be promoted to block pins. |
+| `-starts_with` | Use `POWER` or `GROUND`  for the first placed strap. Defaults to `GROUND`. |
+| `-obstructions` | Layers to add routing blockages to avoid DRC violations. |
+
+Example usage:
+
+```tcl
+define_pdn_grid -name main_grid -pins {metal7} -voltage_domain {CORE TEMP_ANALOG}
+```
+
+### Define Power Grid (Macros)
+
+```tcl
+define_pdn_grid 
+    -macro
+    [-name name]
+    [-grid_over_pg_pins|-grid_over_boundary]
+    [-voltage_domain list_of_domain_names]
+    [-orient list_of_valid_orientations]
+    [-instances list_of_instances]
+    [-cells list_of_cells]
+    [-default]
+    [-halo list_of_halo_values]
+    [-pins list_of_pin_layers]
+    [-starts_with POWER|GROUND]
+    [-obstructions list_of_layers]
+    [-power_switch_cell name]
+    [-power_control signal_name]
+    [-power_control_network STAR|DAISY]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-macro` | The type of grid added as a macro. |
+| `-name` | The name to use when referring to this grid definition. |
+| `-grid_over_pg_pins`, `-grid_over_boundary` | Place the power grid over the power ground pins of the macro (default) or place the power grid over the entire macro.  |
+| `-voltage_domain` | Grid's voltage domain name. Defaults to the last domain created. |
+| `-orient` | For a macro, defines a set of valid orientations. LEF orientations (N, FN, S, FS, E, FE, W and FW) can be used as well as standard geometry orientations (R0, R90, R180, R270, MX, MY, MXR90 and MYR90). Macros with one of the valid orientations will use this grid specification. |
+| `-instances` | For a macro, defines a set of valid instances. Macros with a matching instance name will use this grid specification. |
+| `-cells` | For a macro, defines a set of valid cells. Macros, which are instances of one of these cells, will use this grid specification. |
+| `-default` | For a macro, specifies this is a default grid that can be overwritten. |
+| `-halo` | Specifies the design's default minimum separation of selected macros from other cells. This is only used if the macro does not define halo values in the LEF description. If one value is specified, it will be used on all four sides; if two values are specified, the first will be applied to left/right sides, and the second will be applied to top/bottom sides; if four values are specified, then they are applied to left, bottom, right and top sides respectively (Default: 0). |
+| `-pins` | Defines a list of layers where the power straps will be promoted to block pins. |
+| `-starts_with` | Use `POWER` or `GROUND`  for the first placed strap. Defaults to `GROUND`.|
+| `-obstructions` | Specify the layers to add routing blockages in order to avoid DRC violations. |
+| `-power_switch_cell` | Defines the name of the coarse grain power switch cell to be used wherever the stdcell rail connects to the rest of the power grid. The mesh layers are associated with the unswitched power net of the voltage domain, whereas the stdcell rail is associated with the switched power net of the voltage domain. The placement of a power switch cell connects the unswitched power mesh to the switched power rail through a power switch defined by the `define_power_switch_cell` command. |
+| `-power_control` | Defines the name of the power control signal used to control the switching of the inserted power switches. |
+| `-power_control_network` | Defines the structure of the power control signal network. Choose from STAR or DAISY. If STAR is specified, then the network is wired as a high-fanout net with the power control signal driving the power control pin on every power switch. If DAISY is specified, then the power switches are connected in a daisy-chain configuration - note, this requires that the power switch defined by the `define_power_switch_cell`  command defines an acknowledge pin for the switch. |
+
+Example usage:
+
+```tcl
+define_pdn_grid -macro -name ram          -orient {R0 R180 MX MY} -grid_over_pg_pins  -starts_with POWER -pin_direction vertical
+define_pdn_grid -macro -name rotated_rams -orient {E FE W FW}     -grid_over_boundary -starts_with POWER -pin_direction horizontal
+```
+
+### Define Power Grid for an Existing Routing Solution
+
+```tcl
+define_pdn_grid 
+    -existing
+    [-name name]
+    [-obstructions list_of_layers]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-existing` | Enable use of existing routing solution. |
+| `-name` | The name to use when referring to this grid definition. Defaults to `existing_grid`. |
+| `-obstructions` | The layers to add routing blockages in order to avoid DRC violations. |
+
+Example usage:
+
+```tcl
+define_pdn_grid -name main_grid -existing
+```
+
+### Define Power Switch Cell
+
+Define a power switch cell that will be inserted into a power grid.
+
+```tcl
+define_power_switch_cell 
+    -name name 
+    -control control_pin
+    -power_switchable power_switchable_pin
+    -power unswitched_power_pin
+    -ground ground_pin 
+    [-acknowledge acknowledge_pin_name]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-name` | The name of the power switch cell. |
+| `-control` | The name of the power control port of the power switch cell. |
+| `-switched_power` | The pin's name that outputs the switched power net. |
+| `-power` | The pin's name that connects to the unswitched power net. |
+| `-ground` | The pin's name that connects to the ground net. |
+| `-acknowledge` | The name of the output control signal of the power control switch if it has one. |
+
+Example usage:
+
+```tcl
+define_power_switch_cell -name POWER_SWITCH -control SLEEP -switched_power VDD -power VDDG -ground VSS
+```
+
+### Add Stripes
+
+Defines a pattern of power and ground stripes in a single layer to be added to a power grid.
+
+```tcl
+add_pdn_stripe 
+    -layer layer_name
+    [-grid grid_name]
+    [-width width_value]
+    [-followpins]
+    [-extend_to_core_ring]
+    [-pitch pitch_value]
+    [-spacing spacing_value]
+    [-offset offset_value]
+    [-starts_with POWER|GROUND]
+    [-extend_to_boundary]
+    [-snap_to_grid]
+    [-number_of_straps count]
+    [-nets list_of_nets]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-layer` | The layer name for these stripes. |
+| `-grid` | The grid to which this stripe definition will be added. (Default: Last grid defined by `define_pdn_grid`). |
+| `-width` | Value for the width of the stripe. |
+| `-followpins` | Indicates that the stripe forms part of the stdcell rails, pitch and spacing are dictated by the stdcell rows, and the `-width` is not needed if it can be determined from the cells. |
+| `-extend_to_core_ring` | Extend the stripes to the core PG ring. |
+| `-pitch` | Value for the distance between each power/ground pair. |
+| `-spacing` | Optional specification of the spacing between power/ground pairs within a single pitch defaults to `pitch / 2`. |
+| `-offset` | Value for the offset of the stripe from the lower left corner of the design core area. |
+| `-starts_with` | Use `POWER` or `GROUND`  for the first placed strap. Defaults to `GROUND`. |
+| `-extend_to_boundary` | Extend the stripes to the boundary of the grid. |
+| `-snap_to_grid` | Snap the stripes to the defined routing grid. |
+| `-number_of_straps` | Number of power/ground pairs to add. |
+| `-nets` | Limit straps to just this list of nets. |
+
+Example usage:
+
+```tcl
+add_pdn_stripe -grid main_grid -layer metal1 -followpins
+add_pdn_stripe -grid main_grid -layer metal2 -width 0.17 -followpins
+add_pdn_stripe -grid main_grid -layer metal4 -width 0.48 -pitch 56.0 -offset 2 -starts_with GROUND
+```
+
+### Add Rings
+
+The `add_pdn_ring` command defines power/ground rings around a grid region. The ring structure is built using two layers that are orthogonal to each other. A power/ground pair will be added above and below the grid using the horizontal layer, with another power/ground pair to the left and right using the vertical layer. These four pairs of power/ground stripes form a ring around the specified grid. Power straps on these layers that are inside the enclosed region are extended to connect to the ring.
+
+```tcl
+add_pdn_ring 
+    -layers layer_name
+    -widths width_value|list_of_2_values
+    -spacings spacing_value|list_of_2_values
+    [-grid grid_name]
+    [-core_offsets offset_value]
+    [-pad_offsets offset_value]
+    [-add_connect]
+    [-extend_to_boundary]
+    [-connect_to_pads]
+    [-connect_to_pad_layers layers]
+    [-starts_with POWER|GROUND]
+    [-nets list_of_nets]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-layers` | Specifies the name of the layer for these stripes. |
+| `-widths` | Value for the width of the stdcell rail. |
+| `-spacings` | Optional specification of the spacing between power/ground pairs within a single pitch. (Default: pitch / 2). |
+| `-grid` | Specifies the name of the grid to which this ring defintion will be added. (Default: Last grid created by `define_pdn_grid`). |
+| `-core_offsets` | Value for the offset of the ring from the grid region. |
+| `-pad_offsets` | When defining a power grid for the top level of an SoC, can be used to define the offset of ring from the pad cells. |
+| `-add_connect` | Automatically add a connection between the two layers. |
+| `-extend_to_boundary` | Extend the rings to the grid boundary. |
+| `-connect_to_pads` | The core side of the pad pins will be connected to the ring. |
+| `-connect_to_pad_layers` | Restrict the pad pins layers to this list. |
+| `-starts_with` | Use `POWER` or `GROUND`  for the first placed strap. Defaults to `GROUND`. |
+| `-nets` | Limit straps to just this list of nets. |
+
+Example usage: 
+
+```tcl
+add_pdn_ring -grid main_grid -layer {metal6 metal7} -widths 5.0 -spacings  3.0 -core_offset 5
+```
+
+### Add Connections
+
+The `add_pdn_connect` command is used to define which layers in the power grid are to be connected together. During power grid generation, vias will be added for overlapping power nets and overlapping ground nets. The use of fixed vias from the technology file can be specified or else via stacks will be constructed using VIARULEs. If VIARULEs are not available in the technology, then fixed vias must be used.
+
+```tcl
+add_pdn_connect 
+    -layers list_of_two_layers
+    [-grid grid_name]
+    [-cut_pitch pitch_value]
+    [-fixed_vias list_of_fixed_vias]
+    [-dont_use_vias list_of_vias]
+    [-max_rows rows]
+    [-max_columns columns]
+    [-ongrid ongrid_layers]
+    [-split_cuts split_cuts_mapping]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-layers` | Layers to be connected where there are overlapping power or overlapping ground nets. |
+| `-grid` | Specifies the name of the grid definition to which this connection will be added (Default: Last grid created by `define_pdn_grid`). |
+| `-cut_pitch` | When the two layers are parallel, e.g., overlapping stdcell rails, specify the distance between via cuts. |
+| `-fixed_vias` | List of fixed vias to be used to form the via stack. |
+| `-dont_use_vias` | List or pattern of vias to not use to form the via stack. |
+| `-max_rows` | Maximum number of rows when adding arrays of vias. |
+| `-max_columns` | Maximum number of columns when adding arrays of vias. |
+| `-ongrid` | List of intermediate layers in a via stack to snap onto a routing grid. |
+| `-split_cuts` | Specifies layers to use split cuts on with an associated pitch, for example `{metal3 0.380 metal5 0.500}`. |
+
+Example usage:
+
+```tcl
+add_pdn_connect -grid main_grid -layers {metal1 metal2} -cut_pitch 0.16
+add_pdn_connect -grid main_grid -layers {metal2 metal4}
+add_pdn_connect -grid main_grid -layers {metal4 metal7}
+
+add_pdn_connect -grid ram -layers {metal4 metal5}
+add_pdn_connect -grid ram -layers {metal5 metal6}
+add_pdn_connect -grid ram -layers {metal6 metal7}
+
+add_pdn_connect -grid rotated_rams -layers {metal4 metal6}
+add_pdn_connect -grid rotated_rams -layers {metal6 metal7}
+```
+
+### Repairing Power Grid vias after Detailed Routing
+
+To remove vias which generate DRC violations after detailed placement and routing use `repair_pdn_vias`.
+
+```tcl
+repair_pdn_vias 
+    [-all]
+    [-net net_name]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-all` | Repair vias on all supply nets. |
+| `-net` | Repair only vias on the specified net. |
+
+### Useful Developer Commands
+
+If you are a developer, you might find these useful. More details can be found in the [source file](../src/PdnGen.cc) or the [swig file](PdnGen.i).
+
+| Command Name | Description |
+| ----- | ----- |
+| `name_cmp` | Compare 2 input strings `obj1` and `obj2` if they are equal. |
+| `check_design_state` | Check if the design is loaded. |
+| `get_layer` | Get the layer reference of the layer name. |
+| `get_voltage_domains` | Gets a Tcl list of power domains in design. |
+| `match_orientation` | Checks if a given orientation `orient` is within a list of orientations `orients`. |
+| `get_insts` | Get the Tcl list of instances. |
+| `get_masters` | Get the Tcl list of masters. |
+| `get_one_to_two` | If a Tcl list has one element `{x}`, Tcl list `{x x}` is returned. If a Tcl list of two elements `{y y}`, list as is returned. Otherwise, for any other list lengths, an error is triggered. |
+| `get_one_to_four` | Similar logic for the above function, except the logic only works for lists of length one, two, and four, respectively. All other list lengths trigger errors. |
+| `get_obstructions` | Get the Tcl list of layers. |
+| `get_starts_with` | If value starts with `POWER`, return 1; else if value starts with `GROUND` return 0; else return error. |
+| `get_mterm` | Find master terminal. |
+| `get_orientations` | Get the list of valid orientations. | 
+
+## Example scripts
+
+### Defining a SoC power grid with pads
+
+```
+add_global_connection -net VDD -pin_pattern {^VDD$} -power
+add_global_connection -net VDD -pin_pattern {^VDDPE$}
+add_global_connection -net VDD -pin_pattern {^VDDCE$}
+add_global_connection -net VSS -pin_pattern {^VSS$} -ground
+add_global_connection -net VSS -pin_pattern {^VSSE$}
+
+set_voltage_domain -power VDD -ground VSS
+
+define_pdn_grid -name "Core"
+add_pdn_ring -grid "Core" -layers {metal8 metal9} -widths 5.0 -spacings 2.0 -core_offsets 4.5 -connect_to_pads
+
+add_pdn_stripe -followpins -layer metal1 -extend_to_core_ring
+
+add_pdn_stripe -layer metal4 -width 0.48 -pitch 56.0 -offset 2.0 -extend_to_core_ring
+add_pdn_stripe -layer metal7 -width 1.40 -pitch 40.0 -offset 2.0 -extend_to_core_ring
+add_pdn_stripe -layer metal8 -width 1.40 -pitch 40.0 -offset 2.0 -extend_to_core_ring
+add_pdn_stripe -layer metal9 -width 1.40 -pitch 40.0 -offset 2.0 -extend_to_core_ring
+
+add_pdn_connect -layers {metal1 metal4}
+add_pdn_connect -layers {metal4 metal7}
+add_pdn_connect -layers {metal7 metal8}
+add_pdn_connect -layers {metal8 metal9}
+add_pdn_connect -layers {metal9 metal10}
+
+pdngen
+```
+
+### Sroute
+
+The `add_sroute_connect` command is employed for connecting pins located
+outside of a specific power domain to the power ring, especially in cases where
+multiple power domains are present. During `sroute`, multi-cut vias will be added
+for new connections. The use of fixed vias from the technology file should be
+specified for the connection using the `add_sroute_connect` command. The use
+of max_rows and max_columns defines the row and column limit for the via stack.
+
+```
+add_sroute_connect
+    -layers list_of_2_layers
+    -cut_pitch pitch_value
+    [-net net]
+    [-outerNet outerNet]
+    [-fixed_vias list_of_vias]
+    [-max_rows rows]
+    [-max_columns columns]
+    [-metalwidths metalwidths]
+    [-metalspaces metalspaces]
+    [-ongrid ongrid_layers]
+    [-insts inst]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-net` | The inner net where the power ring exists. |
+| `-outerNet` | The outer net where instances/pins that need to get connected exist. |
+| `-layers` |  The metal layers for vertical stripes within inner power ring. |
+| `-cut_pitch` | Distance between via cuts when the two layers are parallel, e.g., overlapping stdcell rails. (Default:200 200) |
+| `-fixed_vias` | List of fixed vias to be used to form the via stack. |
+| `-max_rows` | Maximum number of rows when adding arrays of vias. (Default:10) |
+| `-max_columns` | Maximum number of columns when adding arrays of vias. (Default:10) |
+| `-metalwidths` | Width for each metal layer. |
+| `-metalspaces` | Spacing of each metal layer. |
+| `-ongrid` | List of intermediate layers in a via stack to snap onto a routing grid. |
+| `-insts` | List of all the instances that contain the pin that needs to get connected with power ring. (Default:nothing) |
+
+#### Examples
+
+```
+add_sroute_connect  -net "VIN" -outerNet "VDD" -layers {met1 met4} -cut_pitch {200 200} -fixed_vias {M3M4_PR_M} -metalwidths {1000 1000} -metalspaces {800} -ongrid {met3 met4} -insts "temp_analog_1.a_header_0"
+
+```
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+Currently the following assumptions are made:
+
+1. The design is rectangular
+1. The input floorplan includes the stdcell rows, placement of all macro blocks and IO pins.
+1. The stdcells rows will be cut around macro placements
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+pdn) about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](../../LICENSE) file.

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+# Pin Placer
+
+Place pins on the boundary of the die on the track grid to minimize net
+wirelengths. Pin placement also creates a metal shape for each pin using
+min-area rules.
+
+For designs with unplaced cells, the net wirelength is computed considering
+the center of the die area as the unplaced cells position.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Define Pin Shape Pattern
+
+The `define_pin_shape_pattern` command defines a pin placement grid on the
+specified layer. This grid has positions inside the die area, not only at
+the edges of the die boundary.
+
+```tcl
+define_pin_shape_pattern 
+    [-layer layer]
+    [-x_step x_step]
+    [-y_step y_step]
+    [-region {llx lly urx ury} | *]
+    [-size {width height}]
+    [-pin_keepout dist]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-layer` | The single top-most routing layer of the placement grid. |
+| `-x_step`, `-y_step` | The distance (in microns) between each valid position on the grid in the x- and y-directions, respectively. |
+| `-region` | The `{llx, lly, urx, ury}` region of the placement grid (in microns). If the `*` is specified, the region will be the entire die area. |
+| `-size` | The width and height (in microns) of the pins assigned to this grid. The centers of the pins are placed on the grid positions. Pins may have half of their shapes outside the defined region. |
+| `-pin_keepout` | The boundary (in microns) around existing routing obstructions that the pins should avoid; this defaults to the `layer` minimum spacing. |
+
+#### Face-to-Face direct-bonding IOs
+
+The `define_pin_shape_pattern` command can be used to place pins in any metal
+layer with the minimum allowed spacing to facilitate 3DIC integration of
+chips using face-to-face packaging technologies. These technologies include
+[micro bumps](https://semiengineering.com/bumps-vs-hybrid-bonding-for-advanced-packaging/)
+and
+[hybrid bonding](https://www.3dincites.com/2018/04/hybrid-bonding-from-concept-to-commercialization/)
+for high density face-to-face interconnect.
+
+### Set IO Pin Constraint
+
+The `set_io_pin_constraint` command sets region constraints for pins according
+to the pin direction or the pin name. This command can be called multiple
+times with different constraints.
+
+You can use the `set_io_pin_constraint` command to restrict pins to the
+pin placement grid created with the `define_pin_shape_pattern` command.
+
+It is possible to use the `-region`, `-group` and `-order` arguments together
+per `set_io_pin_constraint` call, but the `-mirrored_pins` argument should be
+called alone.
+
+```tcl
+set_io_pin_constraint 
+    [-direction direction]
+    [-pin_names names]
+    [-region edge:interval]
+    [-mirrored_pins names]
+    [-group]
+    [-order]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-direction` | Pin direction (`input`, `output`, `inout`, or `feedthrough`). |
+| `-pin_names` | List of names. Only one of (`-direction`, `-pin_names`) should be used in a single call for the `set_io_pin_constraint` command. |
+| `-region` | Syntax is `-region edge:interval`. The `edge` values are (`top\|bottom\|left\|right`). The `interval` can be the whole edge with the wildcard `*` value or a range of values. |
+| `-mirrored_pins` | List of pins that sets pairs of pins that will be symmetrically placed in the vertical or the horizontal edges. The number of pins in this list **must be even**. For example, in `set_io_pin_constraint -mirrored_pins {pin1 pin2 pin3 pin4 pin5 pin6}`, the pins `pin1` and `pin2` will be placed symmetrically to each other. Same for `pin3` and `pin4`, and for `pin5` and `pin6`. |
+| `-group` | Flag places together on the die boundary the pin list defined in `-pin_names,` similar to the `-group_pins` option on the `place_pins` command. |
+| `-order` | Flag places the pins ordered in ascending x/y position and must be used only when `-group` is also used. |
+
+The `edge` values are (up, top, bottom, left, right), where `up` is
+the grid created by `define_pin_shape_pattern`. To restrict pins to the
+pin placement grid defined with `define_pin_shape_pattern` use:
+
+-   `-region up:{llx lly urx ury}` to restrict the pins into a specific
+    region in the grid. The region is defined in microns.
+-   `-region up:*` to restrict the pins into the entire region of the grid.
+
+The `up` option is only available when the pin placement grid is created with
+the `define_pin_shape_pattern` command.
+
+### Clear IO Pin Constraints
+
+The `clear_io_pin_constraints` command clears all the previously-defined
+constraints and pin shape patterns created with `set_io_pin_constraint` or
+`define_pin_shape_pattern`.
+
+```tcl
+clear_io_pin_constraints
+```
+
+### Set Pin Length
+
+The `set_pin_length` command defines the length of all vertical and horizontal
+pins.
+
+```tcl
+set_pin_length 
+    [-hor_length h_length]
+    [-ver_length v_length]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-hor_length` | The length (in microns) of the horizontal pins. |
+| `-ver_length` | The length (in microns) of the vertical pins. |
+
+### Set Pin Extension
+
+The `set_pin_length_extension` command defines the an extension of the length
+of all vertical and horizontal pins. Note that this command may generate pins
+partially outside the die area.
+
+```tcl
+set_pin_length_extension 
+    [-hor_extension h_extension]
+    [-ver_extension v_extension]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-hor_extension` | The length (in microns) for the horizontal pins. |
+| `-ver_extension` | The length (in microns) for the vertical pins. |
+
+### Set Pin Thick Multiplier
+
+The `set_pin_thick_multiplier` command defines a multiplier for the thickness of all
+vertical and horizontal pins.
+
+```tcl
+set_pin_thick_multiplier 
+    [-hor_multiplier h_mult]
+    [-ver_multiplier v_mult]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-hor_multiplier` | The thickness multiplier for the horizontal pins. |
+| `-ver_multiplier` | The thickness multiplier for the vertical pins. |
+
+### Set Simulated Annealing Parameters
+
+The `set_simulated_annealing` command defines the parameters for simulated annealing pin placement.
+
+```tcl
+set_simulated_annealing
+    [-temperature temperature]
+    [-max_iterations iter]
+    [-perturb_per_iter perturbs]
+    [-alpha alpha]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-temperature` | Temperature parameter. The default value is `1.0`, and the allowed values are floats `[0, MAX_FLOAT]`. |
+| `-max_iterations` | The maximum number of iterations. The default value is `2000`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-perturb_per_iter` | The number of perturbations per iteration. The default value is `0`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-alpha` | The temperature decay factor. The default value is `0.985`, and the allowed values are floats `(0, 1]`. |
+
+### Place Individual Pin
+
+The `place_pin` command places a specific pin in the specified location with the specified size.
+It is recommended that individual pins be placed before the `place_pins` command,
+as the routing tracks occupied by these individual pins will be blocked, preventing overlaps.
+
+To place an individual pin:
+
+```tcl
+place_pin 
+    -pin_name pin_name
+    -layer layer
+    -location {x y}
+    [-pin_size {width height}]
+    [-force_to_die_boundary]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-pin_name` | The name of a pin of the design. |
+| `-layer` | The routing layer where the pin is placed. |
+| `-location` | The center of the pin (in microns). |
+| `-pin_size` | The width and height of the pin (in microns). |
+| `-force_to_die_boundary` | When this flag is enabled, the pin will be snapped to the nearest routing track, next to the die boundary. |
+
+### Place All Pins
+
+Use the following command to perform pin placement:
+
+```tcl
+place_pins 
+    -hor_layers h_layers
+    -ver_layers v_layers
+    [-random_seed seed]
+    [-random]
+    [-corner_avoidance length]
+    [-min_distance distance]
+    [-min_distance_in_tracks]
+    [-exclude region]
+    [-group_pins pin_list]
+    [-annealing]
+    [-write_pin_placement file_name]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-hor_layers` | The layers to create the metal shapes of pins placed in horizontal tracks. It can be a single layer or a list of layer names. |
+| `-ver_layers` | The layers to create the metal shapes of pins placed in vertical tracks. It can be a single layer or a list of layer names. |
+| `-corner_avoidance` | The distance (in microns) from each corner within which pin placement should be avoided. |
+| `-min_distance` | The minimum distance between pins on the die boundary. This distance can be in microns (default) or in number of tracks between each pin. |
+| `-min_distance_in_tracks` | Flag that allows setting the min distance in number of tracks instead of microns. |
+| `-exclude` | A region where pins cannot be placed. Either `top|bottom|left|right:edge_interval`, which is the edge interval from the selected edge; `begin:end` for begin-end of all edges. |
+| `-group_pins` | A list of pins to be placed together on the die boundary. |
+| `-annealing` | Flag to enable simulated annealing pin placement. |
+| `-write_pin_placement` | A file with the pin placement generated in the format of multiple calls for the `place_pin` command. |
+
+The `exclude` option syntax is `-exclude edge:interval`. The `edge` values are
+(top|bottom|left|right). The `interval` can be the whole edge, with the `*`
+value, or a range of values. For example, in `place_pins -hor_layers metal2
+-ver_layers metal3 -exclude top:* -exclude right:15-60.5 -exclude left:*-50`
+three intervals are excluded: the whole top edge, the right edge from 15
+microns to 60.5 microns, and the left edge from its beginning to 50 microns.
+
+#### Developer Arguments
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-random_seed` | Specify the seed for random operations. |
+| `-random` | When this flag is enabled, the pin placement is random. |
+
+### Write Pin Placement
+
+Use the following command to write a file with the pin placement in the format of multiple calls for the `place_pin` command:
+
+```tcl
+write_pin_placement file_name
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `file_name` | The name of the file with the pin placement. |
+
+### Useful Developer Commands
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/IOPlacer.cpp) or the [swig file](./src/IOPlacer.i).
+
+| Command Name | Description |
+| ----- | ----- |
+| `parse_edge` | Parse edge (top/bottom/left/right). |
+| `parse_direction` | Parse direction. |
+| `parse_excludes_arg` | Parse excluded arguments. |
+| `parse_group_pins_arg` | Parse group pins arguments. | 
+| `parse_layer_name` | Parse layer name. |
+| `parse_pin_names` | Parse pin names. |
+| `get_edge_extreme` | Get extremes of edge. |
+| `exclude_intervals` | Set exclude interval. |
+| `add_pins_to_constraint` | Add pins to constrained region. |
+| `add_pins_to_top_layer` | Add pins to top layer. | 
+
+
+## Example scripts
+
+Example scripts of `ppl` running on a sample design of `gcd` as follows:
+
+```tcl
+./test/gcd.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## References
+
+- This code depends on [Munkres](src/munkres/README.txt).
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+ioplacer+in%3Atitle)
+about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_psm_README.md

@@ -0,0 +1,148 @@
+# IR Drop Analysis
+
+The IR Drop Analysis module in OpenROAD (`psm`) is based on PDNSim, 
+an open-source static IR analyzer.
+
+Features:
+
+-   Report worst IR drop.
+-   Report worst current density over all nodes and wire segments in the
+    power distribution network, given a placed and PDN-synthesized design.
+-   Check for floating PDN stripes on the power and ground nets.
+-   Spice netlist writer for power distribution network wire segments.
+
+| | |
+| - | - |
+| ![Image 1](doc/current_map.jpg) | ![Image 2](doc/IR_map.jpg) |
+<p style="text-align: center;">(Left): Current Map, (Right): IR drop map</p>
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Analyze Power Grid
+
+```tcl
+analyze_power_grid
+    [-vsrc vsrc_file]
+    [-outfile out_file]
+    [-error_file err_file]
+    [-enable_em]
+    [-em_outfile em_out_file]
+    [-net net_name]
+    [-dx bump_pitch_x]
+    [-dy bump_pitch_y]
+    [-node_density val_node_density]
+    [-node_density_factor val_node_density_factor]
+    [-corner corner]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-vsrc` | File to set the location of the power C4 bumps/IO pins. [Vsrc_aes.loc file](test/Vsrc_aes_vdd.loc) for an example with a description specified [here](doc/Vsrc_description.md). |
+| `-dx`,`-dy` | These arguments set the bump pitch to decide the voltage source location in the absence of a vsrc file. Default bump pitch of 140um used in absence of these arguments and vsrc. |
+| `-net` | Name of the net to analyze, power or ground net name. |
+| `-enable_em` | Report current per power grid segment. |
+| `-outfile` | Write per-instance voltage into the file. |
+| `-em_outfile` | Write the per-segment current values into a file. This option is only available if used in combination with `-enable_em`. |
+| `-voltage` | Sets the voltage on a specific net. If this option is not set, the Liberty file's voltage value is obtained from operating conditions. |
+| `-node_density` | Node density (in microns) on the standard cell rails. It cannot be used together with `-node_density_factor`. |
+| `-node_density_factor` | Factor which is multiplied by standard cell height to determine the node density on the std cell rails. It cannot be used together with `-node_density`. The default value is `5`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-corner` | Corner to use for analysis. | 
+
+### Check Power Grid
+
+```tcl
+check_power_grid -net net_name
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-net` | Name of the net to analyze. Must be a power or ground net name. |
+
+### Write Spice Power Grid
+
+```tcl
+write_pg_spice
+    [-vsrc vsrc_file]
+    [-outfile out_file]
+    [-net net_name]
+    [-dx bump_pitch_x]
+    [-dy bump_pitch_y]
+    [-corner corner]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-vsrc` | File to set the location of the power C4 bumps/IO pins. See [Vsrc_aes.loc file](test/Vsrc_aes_vdd.loc) for an example and its [description](doc/Vsrc_description.md). |
+| `-dx`,`-dy` | Set the bump pitch to decide the voltage source location in the absence of a `vsrc` file. The default bump pitch is 140um if neither these arguments nor a `vsrc` file are given. |
+| `-net` | Name of the net to analyze. Must be a power or ground net name. |
+| `-outfile` | Write per-instance voltage written into the file. |
+| `-corner` | Corner to use for analysis. | 
+
+### Set PDNSim Net voltage
+
+```tcl
+set_pdnsim_net_voltage
+    [-net net_name]
+    [-voltage volt]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-net` | Name of the net to analyze. It must be a power or ground net name. |
+| `-voltage` | Sets the voltage on a specific net. If this option is not given, the Liberty file's voltage value is obtained from operating conditions. |
+
+### Useful Developer Commands
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/pdnsim.cpp) or the [swig file](./src/pdnsim.i).
+
+| Command Name | Description |
+| ----- | ----- |
+| `find_net` | Get a reference to net name. | 
+
+## Example scripts
+
+Example scripts demonstrating how to run PDNSim on a sample design on `aes` as follows:
+
+```tcl
+./test/aes_test_vdd.tcl
+./test/aes_test_vss.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+psm+in%3Atitle)
+about this tool.
+
+## References 
+
+1. PDNSIM [documentation](doc/PDNSim-documentation.pdf)
+1. Chhabria, V.A. and Sapatnekar, S.S. (no date) The-openroad-project/pdnsim: Power Grid Analysis, GitHub. Available at: https://github.com/The-OpenROAD-Project/PDNSim (Accessed: 24 July 2023). [(link)](https://github.com/The-OpenROAD-Project/PDNSim)
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_psm_doc_VOR_description.md

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+# Voltage source location file description
+
+This file specifies the description of the C4 bump configurations file.
+The file is a csv as described below:
+
+```
+<x_coordinate>, <y_coordinate>, <octagonal_c4_bump_edge_length>, <voltage_value>
+```
+
+The x and y coordinate specify the center location of the voltage C4 bumps in
+micro meter.
+
+The octagonal c4_edge_length specifies the edge length of the C4 to determine
+the pitch of the RDL layer in micron
+
+Voltage_value specifies the value of voltage source at the C4 bump. In case
+there is a need to specify voltage drop in micron
+
+## Example file
+
+```
+250,250,20,1.1
+130,170,20,1.1
+370,410,10,1.1
+410,450,10,1.1
+```

data/markdown/OR_userguide/OR_rcx_README.md

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+# Parasitics Extraction
+
+The parasitics extraction module in OpenROAD (`rcx`) is based on the 
+open-source OpenRCX, a Parasitic Extraction (PEX, or RCX) tool that 
+works on OpenDB design APIs.
+It extracts routed designs based on the LEF/DEF layout model.
+
+OpenRCX extracts both Resistance and Capacitance for wires, based on coupling
+distance to the nearest wire and the track density context over and/or under the
+wire of interest, as well as cell
+abstracts.  The capacitance and resistance measurements are based on equations
+of coupling distance interpolated on exact measurements from a calibration
+file, called the Extraction Rules file. The Extraction Rules file (RC technology
+file) is generated once for every process node and corner, using
+a provided utility for DEF wire pattern generation and regression modeling.
+
+OpenRCX stores resistance, coupling capacitance and ground (i.e., grounded) capacitance
+on OpenDB objects with direct pointers to the associated wire and via db
+objects. Optionally, OpenRCX can generate a `.spef` file.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Define Process Corner
+
+```tcl
+define_process_corner 
+    [-ext_model_index index]
+    filename
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-ext_model_index` | Extraction model index. Expects 2 inputs (an index, and corner name). |
+| `filename` | Path to process corner file `rcx_patterns.rules`. |
+
+### Extract Parasitics
+
+The `extract_parasitics` command performs parasitic extraction based on the
+routed design. If there are no information on routed design, no parasitics are
+returned. 
+
+```tcl
+extract_parasitics
+    [-ext_model_file filename]      
+    [-corner_cnt count]            
+    [-max_res ohms]               
+    [-coupling_threshold fF]        
+    [-debug_net_id id]
+    [-lef_res]                     
+    [-cc_model track]             
+    [-context_depth depth]      
+    [-no_merge_via_res]       
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-ext_model_file` | Specify the Extraction Rules file used for the extraction. |
+| `-corner_cnt` | Defines the number of corners used during the parasitic extraction. |
+| `-max_res` | Combines resistors in series up to the threshold value. |
+| `-coupling_threshold` | Coupling below this threshold is grounded. The default value is `0.1`, units are in `fF`, accepted values are floats. |
+| `-debug_net_id` | *Developer Option*: Net ID to evaluate. |
+| `-lef_res` | Override LEF resistance per unit. |
+| `-cc_model` | Specify the maximum number of tracks of lateral context that the tool considers on the same routing level. The default value is `10`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-context_depth` | Specify the number of levels of vertical context that OpenRCX needs to consider for the over/under context overlap for capacitance calculation. The default value is `5`, and the allowed values are integers `[0, MAX_INT]`. |
+| `-no_merge_via_res` | Separates the via resistance from the wire resistance. |
+
+### Write SPEF
+
+The `write_spef` command writes the `.spef` output of the parasitics stored
+in the database.
+
+```tcl
+write_spef
+    [-net_id net_id]                
+    [-nets nets]
+    filename                     
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-net_id` | Output the parasitics info for specific net IDs. |
+| `-nets` | Net name. |
+| `filename` | Output filename. |
+
+### Scale RC
+
+Use the `adjust_rc` command to scale the resistance, ground, and coupling
+capacitance. 
+
+```tcl
+adjust_rc
+    [-res_factor res]               
+    [-cc_factor cc]                
+    [-gndc_factor gndc]          
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-res_factor` | Scale factor for resistance. |
+| `-cc_factor` | Scale factor for coupling capacitance. |
+| `-gndc_factor` | Scale factor for ground capacitance. |
+
+### Comparing SPEF files
+
+The `diff_spef` command compares the parasitics in the reference database `<filename>.spef`.
+The output of this command is `diff_spef.out`
+and contains the RC numbers from the parasitics in the database and the
+`<filename>.spef`, and the percentage RC difference of the two data.
+
+```tcl
+diff_spef
+    [-file filename]                
+    [-r_res]
+    [-r_cap]
+    [-r_cc_cap]
+    [-r_conn]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-file` | Path to the input `.spef` filename. |
+| `-r_res` | Read resistance. |
+| `-r_cap` | Read capacitance. |
+| `-r_cc_cap` | Read coupled capacitance. |
+| `r_conn` | Read connections. |
+
+### Extraction Rules File Generation
+
+The `bench_wires` command produces a layout which contains various patterns
+that are used to characterize per-unit length R and C values. The generated patterns model
+the lateral, vertical, and diagonal coupling capacitances, as well as ground
+capacitance effects. This command generates a .def file that contains a number of wire patterns.
+
+This command is specifically intended for the Extraction Rules file generation only.
+
+```tcl
+bench_wires
+    [-met_cnt mcnt]
+    [-cnt count]
+    [-len wire_len]
+    [-over]
+    [-diag]
+    [-all]
+    [-db_only]
+    [-under_met layer]
+    [-w_list width]
+    [-s_list space]
+    [-over_dist dist]
+    [-under_dist dist]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-met_cnt` | Number of layers used in each pattern. The default value is `-1`, meaning it is not set, and the allowed values are integers `[0, MAX_INT]`. |
+| `-cnt` | Number of wires in each pattern. The default value is `5`, and the default values are integers `[0, MAX_INT]`. |
+| `-len` | Wirelength in microns in the pattern. The default value is `100`, and the allowed values are integers `[0, MAX_INT]`. | 
+| `-all` | Consider all different pattern geometries (`over`, `under`, `over_under`, and `diagonal`). |
+| `-db_only` | Run with db values only. All parameters in `bench_wires` are ignored. |
+| `-under_met` | Consider under metal layer. |
+| `-w_list` | Lists of wire width multipliers from the minimum spacing defined in the LEF. |
+| `-s_list` | Lists of wire spacing multipliers from the minimum spacing defined in the LEF. The list will be the input index on the OpenRCX RC table (Extraction Rules file). |
+| `-over_dist`, `-under_dist` | Consider over and under metal distance respectively. |
+
+### Generate verilog netlist
+
+`bench_verilog` is used after the `bench_wires` command. This command
+generates a Verilog netlist of the generated pattern layout by the `bench_wires`
+command.
+
+This command is optional when running the Extraction Rules generation
+flow. This step is required if the favorite extraction tool (i.e., reference
+extractor) requires a Verilog netlist to extract parasitics of the pattern layout.
+
+
+```tcl
+bench_verilog
+    [filename]                    
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `filename` | Name for the Verilog output file (e.g., `output.v`). |
+
+### Read SPEF
+
+The `bench_read_spef` command reads a `<filename>.spef` file and stores the
+parasitics into the database.
+
+```tcl
+bench_read_spef
+    [filename]                   
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `filename` | Path to the input `.spef` file. |
+
+### Write Rule File
+
+The `write_rules` command writes the Extraction Rules file (RC technology file)
+for OpenRCX. It processes the parasitics data from the layout patterns that are
+generated using the `bench_wires` command, and writes the Extraction Rules file
+with `<filename>` as the output file.
+
+This command is specifically intended for the purpose of Extraction Rules file
+generation.
+
+```tcl
+write_rules
+  [-file filename]           
+  [-dir dir]
+  [-name name]
+  [-pattern pattern]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-file` | Output file name. |
+| `-dir` | Output file directory. |
+| `-name` | Name of rule. |
+| `-pattern` | Flag to write the pattern to rulefile (0/1). | 
+
+## Example scripts
+
+Example scripts demonstrating how to run OpenRCX in the OpenROAD environment
+on sample designs can be found in /test. An example flow test taking a sample design
+from synthesizable RTL Verilog to final-routed layout in an open-source SKY130 technology
+is shown below.
+
+```
+./test/gcd.tcl
+```
+
+Example scripts demonstrating how to run the
+Extraction Rules file generation can be found in this
+[directory](https://github.com/The-OpenROAD-Project/OpenROAD/tree/master/src/rcx/calibration/script).
+
+```
+./calibration/script/generate_patterns.tcl     # generate patterns
+./calibration/script/generate_rules.tcl        # generate the Extraction Rules file
+./calibration/script/ext_patterns.tcl          # check the accuracy of OpenRCX
+```
+
+## Regression tests
+
+There are a set of regression tests in `/test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Extraction Rules File Generation
+
+This flow generates an Extraction Rules file (RC tech file, or RC table) for
+OpenRCX. This file provides resistance and capacitance tables used for RC
+extraction for a specific process corner.
+
+The Extraction Rules file (RC technology file) is generated once for every
+process node and corner automatically.
+
+The detailed documentation can be found [here](doc/calibration.md).
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+rcx)
+about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](../../LICENSE) file.

data/markdown/OR_userguide/OR_rcx_doc_calibration.md

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+# Extraction Rules Generation Flow for OpenRCX
+
+This flow generates the RC tech file for OpenRCX. The RC tech file provides
+resistance and capacitance tables used for RC extraction for a specific process
+corner.
+
+# The flow involves:
+
+A. Running OpenRCX `generate_patterns.tcl` to generate layout patterns.
+
+  - Input: tech LEF
+  - Output: `patterns.def`, `patterns.v`
+  - Script: `generate_patterns.tcl`
+  - Desc: OpenRCX generates many pattern geometries to model various types
+    of capacitance and resistance (i.e., multi-conductor) geometric configurations.
+
+B. Running your favorite extraction tool (i.e., reference extractor) to extract
+    parasitics of the layout patterns.
+
+  - Input: `patterns.def`, `patterns.v` (if required), and additional files
+    required by the reference extractor.
+  - Output: `patterns.spef`
+  - Script: Not provided
+  - Desc: Extract parasitics of the patterns generated by OpenRCX using a reference
+    extractor. This one-time step provides the parasitics of various types of pattern
+    geometries as reference for fitted per-unit length R, C calculation.
+
+C. Running OpenRCX to convert `patterns.spef` to RC tech file.
+
+  - Input: `patterns.spef`
+  - Output: RC tech file
+  - Script: `generate_rules.tcl`
+  - Desc: OpenRCX takes the `.spef` from the reference extractor and performs
+    calculations to produce capacitance and resistance tables for a wide range of
+    wire geometries. The output of this flow is a custom RC tech file for
+    OpenRCX.
+
+D. Benchmarking - test the accuracy of OpenRCX on the patterns layout.
+  - Input: `patterns.def` and RC tech file
+  - Output: `rcx.spef`, `diff_spef.out`
+  - Script: `ext_patterns.tcl`
+  - Desc: Perform parasitic extraction on pattern layout for the calibration
+    using the generated RC tech file. OpenRCX then compares the extracted
+    parasitics with the golden parasitics that had been extracted by the reference extractor
+    in Step (B) above.
+
+## How to run:
+
+1. Go to OpenRCX home directory (`./OpenROAD/src/rcx`).
+
+2. Navigate to calibration folder `cd calibration`
+
+3. Modify the `user_env.tcl` script in the script directory.
+
+  - TECH_LEF: points to the directory of the tech LEF
+  - PROCESS_NODE: the technology node
+  - extRules: the name and the location of the OpenRCX tech file
+
+4. Run the executable script `run.sh` --> run Steps (A) through (D) of the flow above.
+
+  - `source run.sh` or `./run.sh`
+
+5. The OpenRCX RC tech file can be found in the directory that is specified in the extRules variable.

data/markdown/OR_userguide/OR_rmp_README.md

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+# Restructure
+
+The restructure module in OpenROAD (`rmp`) is based on 
+an interface to ABC for local resynthesis. The package allows
+logic restructuring that targets area or timing. It extracts a cloud of logic
+using the OpenSTA timing engine, and passes it to ABC through `blif` interface.
+Multiple recipes for area or timing are run to obtain multiple structures from ABC;
+the most desirable among these is used to improve the netlist.
+The ABC output is read back by a `blif` reader which is integrated to OpenDB.
+`blif` writer and reader also support constants from and to OpenDB. Reading
+back of constants requires insertion of tie cells which should be provided
+by the user as per the interface described below.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+Restructuring can be done in two modes: area or delay.
+
+### Area Mode
+
+```tcl
+restructure 
+    -liberty_file liberty_file
+    -target area
+    -tielo_pin  tielo_pin_name
+    -tiehi_pin  tiehi_pin_name
+    -work_dir  workdir_name
+```
+
+### Timing Mode
+
+```tcl
+restructure 
+    -liberty_file liberty_file
+    -target timing
+    -slack_threshold slack_val
+    -depth_threshold depth_threshold
+    -tielo_pin  tielo_pin_name
+    -tiehi_pin  tiehi_pin_name
+    -work_dir  workdir_name
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-liberty_file` | Liberty file with description of cells used in design. This is passed to ABC. |
+| `-target` | Either `area` or `delay`. In area mode, the focus is area reduction, and timing may degrade. In delay mode, delay is likely reduced, but the area may increase. The default value is `area`. |
+| `-slack_threshold` | Specifies a (setup) timing slack value below which timing paths need to be analyzed for restructuring. The default value is `0`, and the allowed values are floats `[0, MAX_FLOAT]`. |
+| `-depth_threshold` | Specifies the path depth above which a timing path would be considered for restructuring. The default value is `16`, and the allowed values are `[0, MAX_INT]`. |
+| `-tielo_pin` | Tie cell pin that can drive constant zero. The format is `<cell>/<port>`. |
+| `-tiehi_pin` | Tie cell pin that can drive constant one. The format is `<cell>/<port>`. |
+| `-work_dir` | Name of the working directory for temporary files. If not provided, `run` directory would be used. |
+
+## Example scripts
+
+Example scripts on running `rmp` for a sample design of `gcd` as follows:
+
+```tcl
+./test/gcd_restructure.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+restructure)
+about this tool.
+
+## Authors
+
+-   Sanjiv Mathur
+-   Ahmad El Rouby
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_rsz_README.md

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+# Gate Resizer
+
+Gate Resizer commands are described below.  The `resizer` commands stop when
+the design area is `-max_utilization util` percent of the core area. `util`
+is between 0 and 100.  The `resizer` stops and reports an error if the max
+utilization is exceeded.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Set Wire RC
+
+The `set_wire_rc` command sets the resistance and capacitance used to estimate
+delay of routing wires.  Separate values can be specified for clock and data
+nets with the `-signal` and `-clock` flags. Without either `-signal` or
+`-clock` the resistance and capacitance for clocks and data nets are set.
+
+```tcl
+set_wire_rc 
+    [-clock] 
+    [-signal]
+    [-layer layer_name]
+
+or 
+set_wire_rc
+    [-resistance res]
+    [-capacitance cap]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-clock` | Enable setting of RC for clock nets. |
+| `-signal` | Enable setting of RC for signal nets. | 
+| `-layer` | Use the LEF technology resistance and area/edge capacitance values for the layer. This is used for a default width wire on the layer. |
+| `-resistance` | Resistance per unit length, units are from the first Liberty file read, usually in the form of $\frac{resistanceUnit}{distanceUnit}$. Usually kΩ/µm. |
+| `-capacitance` | Capacitance per unit length, units are from the first Liberty file read, usually in the form of $\frac{capacitanceUnit}{distanceUnit}$. Usually pF/µm. |
+
+
+### Set Layer RC
+
+The `set_layer_rc` command can be used to set the resistance and capacitance
+for a layer or via. This is useful if these values are missing from the LEF file,
+or to override the values in the LEF.
+
+```tcl
+set_layer_rc 
+    [-layer layer]
+    [-via via_layer]
+    [-resistance res]
+    [-capacitance cap]
+    [-corner corner]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-layer` | Set layer name to modify. Note that the layer must be a routing layer. |
+| `-via` | Select via layer name. Note that via resistance is per cut/via, not area-based. |
+| `-resistance` | Resistance per unit length, same convention as `set_wire_rc`. |
+| `-capacitance` | Capacitance per unit length, same convention as `set_wire_rc`. |
+| `-corner` | Process corner to use. |
+
+### Estimate Parasitics
+
+Estimate RC parasitics based on placed component pin locations. If there are
+no component locations, then no parasitics are added. The resistance and capacitance
+values are per distance unit of a routing wire. Use the `set_units` command to check
+units or `set_cmd_units` to change units. The goal is to represent "average"
+routing layer resistance and capacitance. If the set_wire_rc command is not
+called before resizing, then the default_wireload model specified in the first
+Liberty file read or with the SDC set_wire_load command is used to make parasitics.
+
+After the `global_route` command has been called, the global routing topology
+and layers can be used to estimate parasitics  with the `-global_routing`
+flag.
+
+```tcl
+estimate_parasitics
+    -placement|-global_routing
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-placement` or `-global_routing` | Either of these flags must be set. Parasitics are estimated based after placement stage versus after global routing stage. |
+
+### Set Don't Use
+
+The `set_dont_use` command removes library cells from consideration by
+the `resizer` engine and the `CTS` engine. `lib_cells` is a list of cells returned by `get_lib_cells`
+or a list of cell names (`wildcards` allowed). For example, `DLY*` says do
+not use cells with names that begin with `DLY` in all libraries.
+
+```tcl
+set_dont_use lib_cells
+unset_dont_use lib_cells
+```
+
+### Set Don't Touch
+
+The `set_dont_touch` command prevents the resizer commands from
+modifying instances or nets.
+
+```tcl
+set_dont_touch instances_nets
+unset_dont_touch instances_nets
+```
+
+### Buffer Ports
+
+The `buffer_ports -inputs` command adds a buffer between the input and its
+loads.  The `buffer_ports -outputs` adds a buffer between the port driver
+and the output port. Inserting buffers on input and output ports makes
+the block input capacitances and output drives independent of the block
+internals.
+
+```tcl
+buffer_ports 
+    [-inputs] 
+    [-outputs] 
+    [-max_utilization util]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-inputs`, `-outputs` | Insert a buffer between the input and load, output and load respectively. The default behavior is `-inputs` and `-outputs` set if neither is specified. |
+| `-max_utilization` | Defines the percentage of core area used. |
+
+### Remove Buffers
+
+Use the `remove_buffers` command to remove buffers inserted by synthesis. This
+step is recommended before using `repair_design` so that there is more flexibility
+in buffering nets. 
+
+```tcl
+remove_buffers
+```
+
+### Repair Design
+
+The `repair_design` command inserts buffers on nets to repair max slew, max
+capacitance and max fanout violations, and on long wires to reduce RC delay in
+the wire. It also resizes gates to normalize slews.  Use `estimate_parasitics
+-placement` before `repair_design` to estimate parasitics considered
+during repair. Placement-based parasitics cannot accurately predict
+routed parasitics, so a margin can be used to "over-repair" the design
+to compensate. 
+
+```tcl
+repair_design 
+    [-max_wire_length max_length]
+    [-slew_margin slew_margin]
+    [-cap_margin cap_margin]
+    [-max_utilization util]
+    [-verbose]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-max_wire_length` | Maximum length of wires (in microns), defaults to a value that minimizes the wire delay for the wire RC values specified by `set_wire_rc`. |
+| `-slew_margin` | Add a slew margin. The default value is `0`, the allowed values are integers `[0, 100]`. |
+| `-cap_margin` | Add a capactitance margin. The default value is `0`, the allowed values are integers `[0, 100]`. |
+| `-max_utilization` | Defines the percentage of core area used. |
+| `-verbose` | Enable verbose logging on progress of the repair. |
+
+### Repair Tie Fanout
+
+The `repair_tie_fanout` command connects each tie high/low load to a copy
+of the tie high/low cell.
+
+```tcl
+repair_tie_fanout 
+    [-separation dist]
+    [-verbose]
+    lib_port
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-separation` | Tie high/low insts are separated from the load by this value (Liberty units, usually microns). |
+| `-verbose` | Enable verbose logging of repair progress. |
+| `lib_port` | Tie high/low port, which can be a library/cell/port name or object returned by `get_lib_pins`. |
+
+### Repair Timing
+
+The `repair_timing` command repairs setup and hold violations.  It
+should be run after clock tree synthesis with propagated clocks.
+Setup repair is done before hold repair so that hold repair does not
+cause setup checks to fail.
+
+The worst setup path is always repaired.  Next, violating paths to
+endpoints are repaired to reduced the total negative slack. 
+
+```tcl
+repair_timing 
+    [-setup]
+    [-hold]
+    [-recover_power percent_of_paths_with_slack]
+    [-setup_margin setup_margin]
+    [-hold_margin hold_margin]
+    [-allow_setup_violations]
+    [-skip_pin_swap]
+    [-skip_gate_cloning]
+    [-repair_tns tns_end_percent]
+    [-max_utilization util]
+    [-max_buffer_percent buffer_percent]
+    [-verbose]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-setup` | Repair setup timing. |
+| `-hold` | Repair hold timing. |
+| `-recover_power` | Set the percentage of paths to recover power for. The default value is `0`, and the allowed values are floats `(0, 100]`. |
+| `-setup_margin` | Add additional setup slack margin. |
+| `-hold_margin` | Add additional hold slack margin. |
+| `-allow_setup_violations` | While repairing hold violations, buffers are not inserted that will cause setup violations unless `-allow_setup_violations` is specified. |
+| `-skip_pin_swap` | Flag to skip pin swap. The default value is `False`, and the allowed values are bools. |
+| `-skip_gate_cloning` | Flag to skip gate cloning. The default value is `False`, and the allowed values are bools. |
+| `-repair_tns` | Percentage of violating endpoints to repair (0-100). When `tns_end_percent` is zero (the default), only the worst endpoint is repaired. When `tns_end_percent` is 100, all violating endpoints are repaired. |
+| `-max_utilization` | Defines the percentage of core area used. |
+| `-max_buffer_percent` | Specify a maximum number of buffers to insert to repair hold violations as a percentage of the number of instances in the design. The default value is `20`, and the allowed values are integers `[0, 100]`. |
+| `-verbose` | Enable verbose logging of the repair progress. |
+
+Use`-recover_power` to specify the percent of paths with positive slack which
+will be considered for gate resizing to save power. It is recommended that
+this option be used with global routing based parasitics. 
+
+### Repair Clock Nets
+
+The `clock_tree_synthesis` command inserts a clock tree in the design
+but may leave a long wire from the clock input pin to the clock tree
+root buffer. The `repair_clock_nets` command inserts buffers in the
+wire from the clock input pin to the clock root buffer.
+
+```tcl
+repair_clock_nets 
+    [-max_wire_length max_wire_length]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-max_wire_length` | Maximum length of wires (in microns), defaults to a value that minimizes the wire delay for the wire RC values specified by `set_wire_rc`. |
+
+### Repair Clock Inverters
+
+The repair_clock_inverters command replaces an inverter in the clock
+tree with multiple fanouts with one inverter per fanout.  This
+prevents the inverter from splitting up the clock tree seen by CTS.
+It should be run before clock_tree_synthesis.
+
+```tcl
+repair_clock_inverters
+```
+
+### Report Design Area
+
+The `report_design_area` command reports the area of the design's components
+and the utilization.
+
+```tcl
+report_design_area
+```
+
+### Report Floating Nets
+
+The `report_floating_nets` command reports nets with only one pin connection.
+
+```tcl
+report_floating_nets 
+    [-verbose]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-verbose` | Print the net names. |
+
+### Useful Developer Commands
+
+If you are a developer, you might find these useful. More details can be found in the [source file](./src/Resizer.cc) or the [swig file](./src/Resizer.i).
+
+| Command Name | Description |
+| ----- | ----- |
+| `repair_setup_pin` | Repair setup pin violation. |
+| `check_parasitics` | Check if the `estimate_parasitics` command has been called. |
+| `parse_time_margin_arg` | Get the raw value for timing margin (e.g. `slack_margin`, `setup_margin`, `hold_margin`) |
+| `parse_percent_margin_arg` | Get the above margin in perentage format. |
+| `parse_margin_arg` | Same as `parse_percent_margin_arg`. |
+| `parse_max_util` | Check maximum utilization. |
+| `parse_max_wire_length` | Get maximum wirelength. |
+| `check_corner_wire_caps` | Check wire capacitance for corner. |
+| `check_max_wire_length` | Check if wirelength is allowed by rsz for minimum delay. |
+| `dblayer_wire_rc` | Get layer RC values. |
+| `set_dblayer_wire_rc` | Set layer RC values. |
+
+## Example scripts
+
+A typical `resizer` command file (after a design and Liberty libraries have
+been read) is shown below.
+
+```tcl
+read_sdc gcd.sdc
+
+set_wire_rc -layer metal2
+
+set_dont_use {CLKBUF_* AOI211_X1 OAI211_X1}
+
+buffer_ports
+repair_design -max_wire_length 100
+repair_tie_fanout LOGIC0_X1/Z
+repair_tie_fanout LOGIC1_X1/Z
+# clock tree synthesis...
+repair_timing
+```
+
+Note that OpenSTA commands can be used to report timing metrics before
+or after resizing the design.
+
+```tcl
+set_wire_rc -layer metal2
+report_checks
+report_tns
+report_wns
+report_checks
+
+repair_design
+
+report_checks
+report_tns
+report_wns
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests). 
+
+Simply run the following script: 
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+resizer)
+about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_stt_OR_flt_README.md

@@ -0,0 +1,19 @@
+# Flute3
+
+Flute3 is an open-source rectilinear Steiner minimum tree heuristic with
+improvements made by UFRGS students and James Cherry. This tool is used
+for the calculation of wirelength in `grt` and `rsz`. 
+
+The version in this repository uses
+CMake and C++ namespace, and has dynamic memory allocation. Flute3 can handle nets with any degree.
+
+## External references (Optional)
+
+The algorithm base is Flute3.1, extracted from the FastRoute4.1 version
+that was received from <yuexu@iastate.edu> on June 15, 2019,
+with the BSD-3 open source license as given in the FastRoute
+[website](https://home.engineering.iastate.edu/~cnchu/FastRoute.html#License).
+
+## License
+
+See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_tap_README.md

@@ -0,0 +1,196 @@
+# Tapcell
+
+Tapcell and endcap insertion.
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Add Tapcell/Endcap
+
+```tcl
+tapcell 
+    [-tapcell_master tapcell_master]
+    [-endcap_master endcap_master]
+    [-distance dist]
+    [-halo_width_x halo_x]
+    [-halo_width_y halo_y]
+    [-tap_nwin2_master tap_nwin2_master]
+    [-tap_nwin3_master tap_nwin3_master]
+    [-tap_nwout2_master tap_nwout2_master]
+    [-tap_nwout3_master tap_nwout3_master]
+    [-tap_nwintie_master tap_nwintie_master]
+    [-tap_nwouttie_master tap_nwouttie_master]
+    [-cnrcap_nwin_master cnrcap_nwin_master]
+    [-cnrcap_nwout_master cnrcap_nwout_master]
+    [-incnrcap_nwin_master incnrcap_nwin_master]
+    [-incnrcap_nwout_master incnrcap_nwout_master]
+    [-tap_prefix tap_prefix]
+    [-endcap_prefix endcap_prefix]
+    [-tbtie_cpp tbtie_cpp]
+    [-no_cell_at_top_bottom]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-tapcell_master` | Master used as a tapcell. |
+| `-endcap_master` | Master used as an endcap. |
+| `-distance` | Distance (in microns) between each tapcell in the checkerboard. |
+| `-halo_width_x` | Horizontal halo size (in microns) around macros during cut rows. |
+| `-halo_width_y` | Vertical halo size (in microns) around macros during cut rows. |
+| `-tap_nwintie_master` | Master cell placed at the top and bottom of|macros and the core area according the row orientation. |
+| `-tap_nwin2_master` | Master cell placed at the top and bottom of macros and the core area according the row orientation. This master should be smaller than `tap_nwintie_master` |
+| `-tap_nwin3_master` | Master cell placed at the top and bottom of macros and the core area according the row orientation. This master should be smaller than `tap_nwin2_master`. |
+| `-tap_nwouttie_master` | Master cell placed at the top and bottom of macros and the core area according the row orientation. |
+| `-tap_nwout2_master` | Master cell placed at the top and bottom of macros and the core area according the row orientation. This master should be smaller than `tap_nwouttie_master`. |
+| `-tap_nwout3_master` | Master cell placed at the top and bottom of macros and the core area according the row orientation | This master should be smaller than `tap_nwout2_master`. |
+| `-incnrcap_nwin_master` | Master cell placed at the corners of macros, according the row orientation. |
+| `-incnrcap_nwout_master` | Master cell placed at the corners of macros, according the row orientation. |
+| `-cnrcap_nwin_master` | Macro cell placed at the corners the core area according the row orientation. |
+| `-cnrcap_nwout_master` | Macro cell placed at the corners the core area according the row orientation. |
+| `-tap_prefix` | Prefix for the tapcell instances. The default value is `TAP_`. |
+| `-endcap_prefix` | Prefix for the endcaps instances. The default value is `PHY_`. |
+| `-tbtie_cpp` | Option is deprecated. |
+| `-no_cell_at_top_bottom` | Option is deprecated. |
+
+The figures below show two examples of tapcell insertion. When only the 
+`-tapcell_master` and `-endcap_master` masters are given, the tapcell placement
+is similar to Figure 1. When the remaining masters are give, the tapcell
+placement is similar to Figure 2.
+
+| <img src="./doc/image/tapcell_example1.svg" width=450px> | <img src="./doc/image/tapcell_example2.svg" width=450px> |
+|:--:|:--:|
+| Figure 1: Tapcell insertion representation | Figure 2:  Tapcell insertion around macro representation |
+
+### Only cutting rows
+
+```tcl
+cut_rows 
+    [-endcap_master endcap_master]
+    [-halo_width_x halo_x]
+    [-halo_width_y halo_y]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-endcap_master` | Master used as an endcap. |
+| `-halo_width_x` | Horizontal halo size (in microns) around macros during cut rows. |
+| `-halo_width_y` | Vertical halo size (in microns) around macros during cut rows. |
+
+### Only adding boundary/endcap cells
+
+Place endcaps into the design, the naming for the arguments to `place_endcaps` is based on the 
+LEF58 `CLASS` specification foe endcaps.
+
+```tcl
+place_endcaps
+    [-corner master]
+    [-edge_corner master]
+    [-endcap masters]
+    [-endcap_horizontal masters]
+    [-endcap_vertical master]
+    [-prefix prefix]
+    [-left_top_corner master]
+    [-right_top_corner master]
+    [-left_bottom_corner master]
+    [-right_bottom_corner master]
+    [-left_top_edge master]
+    [-right_top_edge master]
+    [-left_bottom_edge master]
+    [-right_bottom_edge master]
+    [-left_edge master]
+    [-right_edge master]
+    [-top_edge masters]
+    [-bottom_edge masters]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-prefix` | Prefix to use for the boundary cells. Defaults to "PHY_". |
+| `-corner` | Master for the corner cells on the outer corners. |
+| `-edge_corner` | Master for the corner cells on the inner corners. |
+| `-endcap` | Master used as an endcap. |
+| `-endcap_horizontal` | List of masters for the top and bottom row endcaps. (overrides `-endcap`). |
+| `-endcap_vertical` | Master for the left and right row endcaps. (overrides `-endcap`). |
+| `-left_top_corner` | Master for the corner cells on the outer top left corner. (overrides `-corner`). |
+| `-right_top_corner` | Master for the corner cells on the outer top right corner. (overrides `-corner`). |
+| `-left_bottom_corner` | Master for the corner cells on the outer bottom left corner. (overrides `-corner`). |
+| `-right_bottom_corner` | Master for the corner cells on the outer bottom right corner. (overrides `-corner`). |
+| `-left_top_edge` | Master for the corner cells on the inner top left corner. (overrides `-edge_corner`). |
+| `-right_top_edge` | Master for the corner cells on the inner top right corner. (overrides `-edge_corner`). |
+| `-left_bottom_edge` | Master for the corner cells on the inner bottom left corner. (overrides `-edge_corner`). |
+| `-right_bottom_edge` | Master for the corner cells on the inner bottom right corner. (overrides `-edge_corner`). |
+| `-left_edge` | Master for the left row endcaps. (overrides `-endcap_vertical`). |
+| `-right_edge` | Master for the right row endcaps. (overrides `-endcap_vertical`). |
+| `-top_edge` | List of masters for the top row endcaps. (overrides `-endcap_horizontal`). |
+| `-bottom_edge` | List of masters for the bottom row endcaps. (overrides `-endcap_horizontal`). |
+
+### Only adding tapcells cells
+
+```tcl
+place_tapcells
+    -master tapcell_master
+    -distance dist
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-master` | Master to use for the tapcells. |
+| `-distance` | Distance between tapcells. |
+
+
+### Remove Tapcells/Endcaps
+
+```tcl
+tapcell_ripup
+    -tap_prefix tap_prefix
+    -endcap_prefix endcap_prefix
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-tap_prefix` | Remove tapcells with said prefix. |
+| `-endcap_prefix` | Remove endcaps with said prefix. |
+
+## Example scripts
+
+You can find script examples for both 45nm and 14nm in `./etc/scripts`
+
+```tcl
+./etc/scripts/example_14nm.tcl
+./etc/scripts/example_45nm.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests).
+
+Simply run the following script:
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+tap+in%3Atitle)
+about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.

data/markdown/OR_userguide/OR_upf_README.md

@@ -0,0 +1,185 @@
+# Read UPF Utility
+
+This module contains functionality to read, and modify information
+from Unified Power Format (UPF) files. 
+
+## Commands
+
+```{note}
+- Parameters in square brackets `[-param param]` are optional.
+- Parameters without square brackets `-param2 param2` are required.
+```
+
+### Read UPF
+
+Sources the UPF file. 
+
+```tcl
+read_upf
+    -file file
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-file` | Path to `.upf` file. |
+
+### Create Power Domain
+
+```tcl
+create_power_domain
+    [-elements elements]
+    name 
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-elements` | List of module paths that belong this this domain OR `*` for top domain. |
+| `name` | Domain name. |
+
+### Create Logic Port
+
+```tcl
+create_logic_port
+    [-direction direction]
+    port_name
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-direction` | Direction of the port (`in`, `out`, `inout`). |
+| `port_name` | Port name. |
+
+### Create Power Switch
+
+```tcl
+create_power_switch
+    [-domain domain]
+    [-output_supply_port output_supply_port]
+    [-input_supply_port input_supply_port]
+    [-control_port control_port]
+    [-on_state on_state]
+    name
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-domain` | Power domain name. |
+| `-output_supply_port` | Output supply port of the switch. |
+| `-input_supply_port` | Input supply port of the switch. |
+| `-control_port` | Control port on the switch. |
+| `-on_state` | One of {`state_name`, `input_supply_port`, `boolean_expression`}. |
+| `name` | Power switch name. |
+
+### Create or Update Isolation Strategy
+
+```tcl 
+set_isolation
+    [-domain domain]
+    [-applies_to applies_to]
+    [-clamp_value clamp_value]
+    [-isolation_signal isolation_signal]
+    [-isolation_sense isolation_sense]
+    [-location location]
+    [-update]
+    name
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-domain` | Power domain |
+| `-applies_to` | Restricts the strategy to apply one of these (`inputs`, `outputs`, `both`). |
+| `-clamp_value` | Value the isolation can drive (`0`, `1`). |
+| `-isolation_signal` | The control signal for this strategy. |
+| `-isolation_sense` | The active level of isolation control signal. |
+| `-location` | Domain in which isolation cells are placed (`parent`, `self`, `fanout`). |
+| `-update` | Only available if using existing strategy, will error if the strategy doesn't exist. |
+| `name` | Isolation strategy name. |
+
+### Set Interface cell
+
+```tcl 
+use_interface_cell
+    [-domain domain]
+    [-strategy strategy]
+    [-lib_cells lib_cells]
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-domain` | Power domain name. |
+| `-strategy` | Isolation strategy name. |
+| `-lib_cells` | List of lib cells that could be used. |
+
+### Set Domain Area
+
+```tcl
+set_domain_area
+    domain_name
+    -area {llx lly urx ury}
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `domain_name` | Power domain name. |
+| `-area` | x-/y- coordinates in microns for the lower left and upper right corners of the power domain area. |
+
+
+### Map existing power switch
+
+```tcl 
+map_power_switch
+    [-switch_name_list switch_name_list]
+    [-lib_cells lib_cells]
+    [-port_map port_map]
+```
+
+#### Options
+
+| Switch Name | Description | 
+| ----- | ----- |
+| `-switch_name_list` |  A list of switches (as defined by create_power_switch) to map. |
+| `-lib_cells` | A list of library cells that could be mapped to the power switch |
+| `-port_map` | A map that associates model ports defined by create_power_switch to logical ports |
+
+## Example scripts
+
+Example script demonstrating how to run `upf` related commands can be found here:
+
+```tcl
+./test/upf_test.tcl
+```
+
+## Regression tests
+
+There are a set of regression tests in `./test`. For more information, refer to this [section](../../README.md#regression-tests). 
+
+Simply run the following script: 
+
+```shell
+./test/regression
+```
+
+## Limitations
+
+## FAQs
+
+Check out [GitHub discussion](https://github.com/The-OpenROAD-Project/OpenROAD/discussions/categories/q-a?discussions_q=category%3AQ%26A+upf)
+about this tool.
+
+## License
+
+BSD 3-Clause License. See [LICENSE](LICENSE) file.